AT89C51CC03C-SLRIM Atmel, AT89C51CC03C-SLRIM Datasheet - Page 35
AT89C51CC03C-SLRIM
Manufacturer Part Number
AT89C51CC03C-SLRIM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-SLRIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CSLRTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Entering Power-Down Mode
Exiting Power-Down Mode
Figure 19. Power-Down Exit Waveform Using INT1:0#
4182E–CAN–05/04
INT1:0#
OSC
Active phase
To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters
the Power-Down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
Note:
There are two ways to exit the Power-Down mode:
1. Generate an enabled external interrupt.
Note:
Note:
2. Generate a reset.
Note:
Note:
–
–
If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until
VCC is restored to the normal operating level.
The AT89C51CC03 provides capability to exit from Power-Down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (see Figure 19). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-Down mode.
The external interrupt used to exit Power-Down mode must be configured as level sensi-
tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The exe-
cution will only resume when the interrupt is deasserted.
Exit from power-down by external interrupt does not affect the
content.
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-Down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the AT89C51CC03 and
vectors the CPU to address 0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated the Power-Down
mode should not write to a Port pin or to the external RAM.
Exit from power-down by reset redefines all the
RAM content.
Power-down phase
Oscillator restart phase
SFRs
, but does not affect the internal
Active phase
AT89C51CC03
SFRs
nor the internal RAM
35
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