AT89C51CC03C-SLRIM Atmel, AT89C51CC03C-SLRIM Datasheet - Page 84
AT89C51CC03C-SLRIM
Manufacturer Part Number
AT89C51CC03C-SLRIM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-SLRIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CSLRTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Watchdog Timer During
Power-down Mode and
Idle
Register
84
AT89C51CC03
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode, the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig-
nificantly different. The interrupt shall be held low long enough for the oscillator to
stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started
until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is
best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
AT89C51CC03 while in Idle mode, the user should always set up a timer that will period-
ically exit Idle, service the WDT, and re-enter Idle mode.
Table 44. WDTPRG Register
WDTPRG (S:A7h)
Watchdog Timer Duration Programming Register
Reset Value = XXXX X000b
Number
Bit
7
–
7
6
5
4
3
2
1
0
Mnemonic Description
Bit
S2
S1
S0
6
–
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Watchdog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.
Watchdog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.
Watchdog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.
5
–
4
–
3
–
S2
2
4182E–CAN–05/04
S1
1
S0
0
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