PIC12F675-E/SN Microchip Technology, PIC12F675-E/SN Datasheet - Page 17
PIC12F675-E/SN
Manufacturer Part Number
PIC12F675-E/SN
Description
IC MCU CMOS 1K FLASH W/AD 8-SOIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
4.PIC12F675-ESN.pdf
(132 pages)
Specifications of PIC12F675-E/SN
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-SOIC (3.9mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 53270-913
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.0
The
Configuration bits. These bits can be programmed
(reads ‘0’) or left unchanged (reads ‘1’) to select
various device configurations.
REGISTER 3-1:
© 2005 Microchip Technology Inc.
bit 13
bit 13-12 BG<1:0>: Band Gap Calibration bits
bit 11-9 Unimplemented: Read as ‘0’
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/P-1 R/P-1
BG1
PIC12F629/675/PIC16F630/676
CONFIGURATION WORD
BG0
00 = Lowest band gap voltage
...
11 = Highest band gap voltage
CPD: Code Protection Data bit
1 = Data memory is not protected
0 = Data memory is external read protected
CP: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
BODEN: Brown-out Detect Enable bit
1 = BOD enabled
0 = BOD disabled
MCLRE: MCLR Pin Function Select bit
1 = MCLR pin is MCLR function
0 = MCLR pin is alternate function, MCLR function is internally disabled
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Low-power crystal on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
001 = XT oscillator: Crystal/resonator on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
010 = HS oscillator: High-speed crystal/resonator on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
011 = EC: I/O function on GP4/T1G/OSC2/CLKOUT, CLKIN on GP5/T1CKI/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on GP4/T1G/OSC2/CLKOUT, I/O function on GP5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on GP4/T1G/OSC2/CLKOUT, I/O function on GP5/T1CKI/OSC1/
110 = RC oscillator: I/O function on GP4/T1G/OSC2/CLKOUT, RC on GP5/T1CKI/OSC1/CLKIN
111 = RC oscillator: CLKOUT function on GP4/T1G/OSC2/CLKOUT, RC on GP5/T1CKI/OSC1/CLKIN
Legend:
R = Readable bit
-n = Value at POR
Note 1: Enabling Brown-out Detect Reset Enable does not automatically enable the Power-up Timer
CLKIN
U-0
2: The Band Gap Calibration bits must be read and preserved, then replaced by the user during any
3: GP4 and GP5 apply to PIC12F629/675 only. For PIC16F630/676, use RA4 and RA5,
—
Enable (PWRTE).
bulk erase operation.
respectively.
CONFIGURATION WORD FOR PIC12F629/675/PIC16F630/676
U-0
—
U-0
—
W = Writable bit
‘1’ = Bit is set
R/P-1 R/P-1
CPD
PIC12F629/675/PIC16F630/676
has
CP
(1)
(2)
several
(3)
(1)
BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
R/P-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/P-1
R/P-1
R/P-1
x = Bit is unknown
R/P-1
DS41191D-page 17
R/P-1
R/P-1
bit 0