PIC24F04KA200-I/P Microchip Technology, PIC24F04KA200-I/P Datasheet - Page 97
PIC24F04KA200-I/P
Manufacturer Part Number
PIC24F04KA200-I/P
Description
IC PIC MCU FLASH 512KX4 14-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA200-I/P
Core Size
16-Bit
Program Memory Size
4KB (1.375K x 24)
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Number Of I /o
12
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Controller Family/series
PIC24
No. Of I/o's
12
Ram Memory Size
512Byte
Cpu Speed
32MHz
No. Of Timers
3
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24F04KA200-I/P
Manufacturer:
MICROCHIP
Quantity:
576
- PIC24F04KA201-ISS PDF datasheet
- PIC24F04KA201-ISS PDF datasheet #2
- PIC24F04KA201-ISS PDF datasheet #3
- PIC24F04KA201-ISS PDF datasheet #4
- Current page: 97 of 224
- Download datasheet (4Mb)
REGISTER 9-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0
DSEN
U-0
—
2:
All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Preliminary
(2)
PIC24F04KA201 FAMILY
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(1)
U-0
U-0
—
—
x = Bit is unknown
DSBOR
R/W-0
U-0
—
(2)
DS39937B-page 95
R/C-0, HS
RELEASE
U-0
—
bit 8
bit 0
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