DSPIC30F3010-20I/ML Microchip Technology, DSPIC30F3010-20I/ML Datasheet - Page 17
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DSPIC30F3010-20I/ML
Manufacturer Part Number
DSPIC30F3010-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3010-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301020IML
© 2010 Microchip Technology Inc.
Note:
Note:
Work around 2:
Instead of executing a PWRSAV #0 instruction to
put the device into Sleep mode, perform a clock
switch to the 512 kHz Low-Power RC (LPRC)
Oscillator with a 64:1 postscaler mode. This
enables the device to operate at 0.002 MIPS,
thereby
consumption of the device. Similarly, instead of
using an interrupt to wake-up the device from
Sleep mode, perform another clock switch back to
the original oscillator source to resume normal
operation. Depending on the device, refer to
Section 7. “Oscillator” (DS70054) or Section
29. “Oscillator” (DS70268) in the “dsPIC30F
Family Reference Manual” (DS70046) for more
details on performing a clock switch operation.
Work around 3:
Instead of executing a PWRSAV #0 instruction to
put the device into Sleep mode, perform a clock
switch to the 32 kHz Low-Power (LP) Oscillator
with a 64:1 postscaler mode. This enables the
device to operate at 0.000125 MIPS, thereby
significantly reducing the current consumption of
the device. Similarly, instead of using an interrupt
to wake-up the device from Sleep mode, perform
another clock switch back to the original oscillator
source to resume normal operation. Depending on
the device, refer to Section 7. “Oscillator”
(DS70054)
(DS70268) in the “dsPIC30F Family Reference
Manual” (DS70046) for more details on performing
a clock switch operation.
Affected Silicon Revisions
A0
X
The above work around is recommended
for users for whom application hardware
changes are not possible.
The above work around is recommended
for users for whom application hardware
changes are possible, and also for users
whose
includes a 32 kHz LP Oscillator crystal.
A1
X
significantly
or
A2
application
Section
reducing
hardware
29.
the
“Oscillator”
already
current
28. Module: QEI
29. Module: QEI
30. Module: ADC
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt
should be generated after an input pulse on the
QEA input. This interrupt is not generated in the
affected silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the QEIx-
CON register are set, the POSCNT counter
should not increment but erroneously does, and
if allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while running the QEI in Timer Gated Accumulation
mode, initialize MAXCNT = 0.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable regis-
ter (PMDx), prior to executing a PWRSAV #0
instruction.
Affected Silicon Revisions
A0
A0
A0
X
X
X
A1
A1
A1
dsPIC30F3010/3011
X
X
X
PD
) may exceed the specifications listed
A2
A2
A2
X
X
X
PD
DS80449D-page 17
specifications