PIC16C774-I/L Microchip Technology, PIC16C774-I/L Datasheet - Page 43
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PIC16C774-I/L
Manufacturer Part Number
PIC16C774-I/L
Description
IC MCU OTP 4KX14 A/D PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C773SO.pdf
(201 pages)
3.PIC16C774P.pdf
(13 pages)
4.PIC16C774P.pdf
(16 pages)
Specifications of PIC16C774-I/L
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164309 - MODULE SKT FOR PM3 44PLCCISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16C774-04I/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C774-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
5.2
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal.
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1
TABLE 5-2
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
Note 1: Higher capacitance increases the stability
Address
0Bh,8Bh,
10Bh,18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Note 1:
Osc Type
1999 Microchip Technology Inc.
LP
These values are for design guidance only.
2: Since each resonator/crystal has its own
Timer1 Oscillator
of oscillator but also increases the start-up
time.
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
These bits are reserved on the 28-pin devices, always maintain these bits clear.
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Name
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
100 kHz
200 kHz
32 kHz
Freq
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
PSPIF
PSPIE
Table 5-1
Bit 7
GIE
—
(1)
(1)
33 pF
15 pF
15 pF
PEIE
ADIF
ADIE
Bit 6
C1
—
shows the capacitor
T1CKPS1
RCIF
RCIE
Bit 5
T0IE
Advance Information
33 pF
15 pF
15 pF
20 PPM
20 PPM
20 PPM
C2
T1CKPS0
INTE
TXIE
Bit 4
TXIF
T1OSCEN
SSPIF
SSPIE
RBIE
Bit 3
5.3
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
Note:
T1SYNC
CCP1IE
CCP1IF
Bit 2
T0IF
Timer1 Interrupt
Resetting Timer1 using a CCP Trigger
Output
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR1CS
TMR2IE
TMR2IF
INTF
Bit 1
PIC16C77X
TMR1ON
TMR1IF
TMR1IE
RBIF
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
DS30275A-page 43
Value on:
POR,
BOR
Value on
all other
resets