AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1364
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
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Quantity:
996
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47.14 DDRSDRC Timings
47.15 Peripheral Timings
47.15.1
47.15.1.1
1364
Master Write Mode
Master Read Mode
Slave Read Mode
Slave Write Mode
AT91SAM9M10
SPI
Maximum SPI Frequency
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR (1.8V, 30pF on data/control, 10pF on CK)
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
Tcyc = 5.0 ns, Fmax = 125 MHz
Tcyc = 6.0 ns, Fmax = 110 MHz
Tcyc = 7.5 ns, Fmax = 95 MHz
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
T
DataFlash (AT45DB642D), T
In the formula above, F
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by
setup and hold timings SPI
the pad limit, the limit in slave read mode is given by SPCK pad.
For 3.3V I/O domain and SPI6, F
before sampling data.
f
f
SPCK
SPCK
valid
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
Max
Max
=
=
Section 47.9
2
--------------------------------------------------------
SPI
-------------------------------------------------------- -
SPI
(or SPI
0
6
orSPI
orSPI
5
) timing. Since it gives a maximum frequency above the maximum pad
SPCK
1
1
“I/Os”), the max SPI frequency is the one from the pad.
3
9
Max = 38.5 MHz @ VDDIO = 3.3V.
7
+
+
/SPI
valid
T
T
valid
setup
(orT
8
SPCK
(or SPI
v
Max = 33 MHz. T
) is 12 ns Max.
10
/SPI
11
). Since this gives a frequency well above
setup
is the setup time from the master
6355B–ATARM–21-Jun-10
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