AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 194

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 21-9. No Setup, No Hold On NRD and NCS Read Signals
21.8.1.5
21.8.2
21.8.2.1
194
AT91SAM9M10
Read Mode
Null Pulse
Read is Controlled by NRD (READ_MODE = 1):
NBS0,NBS1,
NBS2,NBS3,
A0, A1
D[31:0]
A[25:2]
MCK
NRD
NCS
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register
of the corresponding chip select indicates which signal of NRD and NCS controls the read
operation.
Figure 21-10
read data is available t
NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate
that data is available with the rising edge of NRD. The SMC samples the read data internally on
the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro-
grammed waveform of NCS may be.
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
shows the waveforms of a read operation of a typical asynchronous RAM. The
PACC
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
6355B–ATARM–21-Jun-10