AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 231
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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22.3
22.3.1
6355B–ATARM–21-Jun-10
Product Dependencies
SDR-SDRAM Initialization
The addresses given are for example purposes only. The real address depends on implementa-
tion in the product.
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized
by the following sequence:
A minimum pause of 200 μs is provided to precede any signal toggle.
Note:
1. Program the memory device type into the Memory Device Register (see
2. Program the features of the SDR-SDRAM device into the Timing Register (asynchro-
3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength
4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode
5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks
6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command
7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-
8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS)
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
on page
nous timing (trc, tras, etc.)), and into the Configuration Register (number of columns,
rows, banks, cas latency) (see
and
(DS) and partial array self refresh (PASR) must be set in the Low-power Register (see
Section 22.7.7 on page
Register, the application must set Mode to 1 in the Mode Register (See
on page
this command. Now the clock which drives SDR-SDRAM device is enabled.
precharge command into Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command.
(CBR) into Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion eight times to acknowledge these commands.
SDRAM devices, in particular CAS latency and burst length. The application must set
Mode to 3 in the Mode Register (see
access to the SDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The appli-
cation must set Mode to 5 in the Mode Register (see
perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example,
with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
write access should be done at the address 0x20800000.
Section 22.7.1 on page
to acknowledge this command.
This address is for example purposes only. The real address is dependent on implementation in
the product.
Section 22.7.5 on page
Section 22.7.1 on page
271).
260). Perform a write access to any SDR-SDRAM address to acknowledge
Section 22.7.1 on page
269).
260) and perform a write access at any location in the SDRAM
267).
260).Performs a write access to any SDR-SDRAM loca-
Section 22.7.3 on page
Section 22.7.1 on page
260). Perform a write access to any SDR-
Section 22.7.1 on page
262,
Section 22.7.4 on page 265
AT91SAM9M10
260) and perform a write
Section 22.7.1
Section 22.7.8
260) and
231
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