AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 270
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
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Quantity:
996
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• TCR: Temperature Compensated Self Refresh
Reset value is “0”.
This field is unique to Low-power SDRAM. It is used to program the refresh interval during self refresh mode, depending
on the case temperature of the low-power SDRAM.
The values of this field are dependent on Low-power SDRAM devices.
After the initialization sequence, as soon as TCR field is modified, Extended Mode Register is accessed automatically and
TCR bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh
command and a pending read or write access.
• DS: Drive Strength
Reset value is “0”.
This field is unique to Low-power SDRAM. It selects the driver strength of SDRAM output.
After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and
DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh
command and a pending read or write access.
• TIMEOUT
Reset value is “00”.
This field defines when low-power mode is enabled.
• APDE: Active Power Down Exit Time
Reset value is “1”.
This mode is unique to DDR2-SDRAM devices. This mode allows to determine the active power-down mode, which
determines performance versus power saving.
0 = Fast Exit
1 = Slow Exit
After the initialization sequence, as soon as APDE field is modified Extended Mode Register, located in the memory of the
external device, is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done
before entering in self refresh mode or during a refresh command and a pending read or write access
• UPD_MR: Update Load Mode Register and Extended Mode Register
Reset value is “0”.
This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This
update is function of DDRSDRC integration in a system. DDRSDRC can either share or not share an external bus with
another controller.
6355B–ATARM–21-Jun-10
00
01
10
11
00
01
10
11
The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
Reserved
Update is disabled.
DDRSDRC shares external bus. Automatic update is done during an refresh command and a pending read or write access in SDRAM device.
DDRSDRC does not share external bus. Automatic update is done before entering in self refresh mode.
Reserved
AT91SAM9M10
270
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