AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 461
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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30.4.12
6355B–ATARM–21-Jun-10
Programmable I/O Delays
If a write access in a write-protected register is detected, then the WPVS flag in the PIO Write
Protect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is automatically reset after reading the PIO Write Protect Status Register
(PIO_WPSR).
List of the write-protected registers:
The PIO interface consists of a series of signals driven by peripherals or directly by sofware. The
simultaneous switching outputs on these busses may lead to a peak of current in the internal
and external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be
adjusted independently for pad buffers by means of configuration registers, PIO_DELAY.
For each I/O, the additional programmable delays range from 0 to 4 ns (Worst Case PVT). The
delay can differ between IOs supporting this feature. The delay can be modified according to
programming for each I/O. The minimum additional delay that can be programmed on a PAD
supporting this feature is 1/16 of the maximum programmable delay.
Only PADs PC[12], PC[7:2], PA[30:23] and PA[9:2] can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of
the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field, the prop-
agation delay of the corresponding pad is maximal.
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“PIO Enable Register” on page 466
“PIO Disable Register” on page 466
“PIO Output Enable Register” on page 467
“PIO Output Disable Register” on page 468
“PIO Input Filter Enable Register” on page 469
“PIO Input Filter Disable Register” on page 469
“PIO Set Output Data Register” on page 470
“PIO Clear Output Data Register” on page 471
“PIO Multi-driver Enable Register” on page 474
“PIO Multi-driver Disable Register” on page 475
“PIO Pull Up Disable Register” on page 476
“PIO Pull Up Enable Register” on page 476
“PIO Peripheral A Select Register” on page 477
“PIO Peripheral B Select Register” on page 478
“PIO Output Write Enable Register” on page 479
“PIO Output Write Disable Register” on page 479
AT91SAM9M10
461
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