AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 579
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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32.7.8.23
Figure 32-52. Master Node with PDC (PDCM=1)
6355B–ATARM–21-Jun-10
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
Master Node Configuration
(DMA)
PDC
The PDC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDC
always writes in the Transmit Holding register (US_THR) and it always reads in the Receive
Holding register (US_RHR). The size of the data written or read by the PDC in the USART is
always a byte.
The user can choose between two PDC modes by the PDCM bit in the LIN Mode register
(US_LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR).
Because the PDC transfer size is limited to a byte, the transfer is split into two accesses.
During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are
written. During the second access the 8-bit DLC field is written.
the user in the LIN Mode register (US_LINMR).
APB bus
RXRDY
NODE ACTION = PUBLISH
LIN CONTROLLER
USART3
WRITE BUFFER
READ BUFFER
IDENTIFIER
CHKTYP
PARDIS
CHKDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
(DMA)
PDC
AT91SAM9M10
APB bus
RXRDY
TXRDY
NODE ACTION = SUBSCRIBE
LIN CONTROLLER
USART3
579
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