AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 612

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• DRIFT: Drift compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
32.8.16
Name:
Access:
• NACT: LIN Node Action
• PARDIS: Parity Disable
0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node
configuration, the parity is checked automatically.
1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.
• CHKDIS: Checksum Disable
0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the check-
sum is checked automatically.
1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked.
• CHKTYP: Checksum Type
0: LIN 2.0 “Enhanced” Checksum
1: LIN 1.3 “Classic” Checksum
612
WKUPTYP
0
0
1
1
31
23
15
–
–
7
NACT
AT91SAM9M10
USART3 LIN Mode Register
0
1
0
1
FSDIS
30
22
14
US_LINMR
Read-write
–
–
6
Mode Description
PUBLISH: The USART transmits the response.
SUBSCRIBE: The USART receives the response.
IGNORE: The USART does not transmit and does not receive the response.
Reserved
DLM
29
21
13
–
–
5
CHKTYP
28
20
12
–
–
4
DLC
CHKDIS
27
19
11
–
–
3
PARDIS
26
18
10
–
–
2
25
17
–
–
9
1
6355B–ATARM–21-Jun-10
NACT
PDCM
24
16
–
8
0