Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet
Z16F2810VH20EG
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Z16F2810VH20EG
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Z16F2810VH20EG Summary of contents
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... An Company High Performance Microcontrollers ® ZNEO Z16F Series Product Specification PS022008-0810 ® Copyright ©2010 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, ZNEO, and Z16F are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...
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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Date Revision Level Section August 08 ...
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July 05 External 2006 General-Purpose Input/ Output, Option Debugger, and Electrical Characteristics Ordering Information January 04 All 2006 All Signal and Pin Descriptions, Controller, and Functions Ordering Information PS022008-0810 Interface, Modifications done in the following chapters: External Interface, GPIO, DMA ...
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Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Input/Output Memory Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CPU Control Registers . ...
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Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 90 IRQ1 Enable High and Low Bit ...
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PWM Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIN-UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LIN-UART Baud Rate High and Low Byte Registers ...
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I C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Comparison with Master Mode only I ...
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ADC0 Control Register ...
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DMA Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Auto-Baud Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Oscillator Control ...
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... Introduction ® Zilog’s ZNEO Z16F family of products are optimized for demanding applications. The ZNEO line of Zilog Features ZNEO family of products include the following features: • 20 MHz ZNEO CPU • 128 KB internal Flash memory with 16-bit access and In-Circuit Programming (ICP) • ...
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On-Chip Debugger (OCD) • Voltage Brownout (VBO) protection • Power-On Reset (POR) • 2 3.6 V operating voltage with 5 V-tolerant inputs • 0 °C to +70 °C standard temperature and ...
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... Pipelined instructions: Fetch, Decode, and Execute. For more information on ZNEO CPU, refer to ZNEO CPU User Manual (UM0188) available for download at www.zilog.com. External Interface The external interface allows seamless connection to external memory and peripherals. A 24-bit address bus and a selectable 8-bit or 16-bit data bus allows parallel access up to ...
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... ZNEO Peripheral Overview Zilog’s ZNEO peripherals are briefly described below. 10-Bit Analog-to-Digital Converter with Programmable Gain Amplifier The ADC converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from 12 different analog input sources. Analog Comparator It features an on-chip analog comparator with external input pins. ...
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DMA Controller The ZNEO features a 4-channel DMA for efficient transfer of data between peripherals and/or memories. The DMA controller supports data transfers to and from both internal and external devices. Pulse Width Modulator The ZNEO features a flexible PWM ...
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PS022008-0810 ZNEO Z16F Series Product Specification 6 Introduction ...
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Signal and Pin Descriptions ® The ZNEO Z16F Series products are available in various package styles and pin configurations. This chapter describes the signals and available pin configurations for each package style. For more information on the physical package specifications, ...
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PA0 / T0IN/T0OUT 49 PD2 / PWMH2 PC2 / SS RESET VDD PE4 PE3 VSS 56 PE2 PE1 PE0 VSS PD1 / PWML1 PD0 / PWMH1 XOUT XIN 64 1 Figure 2. Z16F2810 in 64-Pin Low-Profile Quad Flat Package ...
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PA0 / T0IN/T0OUT 10 PD2 / PWMH2 PC2 / SS RESET VDD PE4 PE3 VSS 18 PE2 PE1 PE0 VSS VDD PD1 / PWML1 PD0 / PWMH1 XOUT XIN 26 27 Figure 3. Z16F2810 in 68-Pin Plastic Leaded Chip ...
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PA0 / T0IN/T0OUT / DMA0REQ PD2 / PWMH2 / ADR22 PC2 / SS / CS4 PF6 / ADR6 5 RESET VDD PF5 / ADR5 PF4 / ADR4 PF3 / ADR3 10 PE4 / DATA4 PE3 / DATA3 VSS ...
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PA0 /T0IN/T0OUT/ DMA0REQ PD2 / PWMH2 / ADR22 PC2 / SS / CS4 PF6 / ADR6 5 RESET VDD PF5 / ADR5 PF4 / ADR4 PF3 / ADR3 10 PE4 / DATA4 PE3 / DATA3 VSS PE2 / ...
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Signal Descriptions Table 2 describes the ZNEO signals. To determine the signals available for the specific package styles, see are multiplexed with GPIO pins. These signals are available as alternate functions on the GPIO pins. For more details on the ...
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Table 2. Signal Descriptions (Continued) Signal Mnemonic I CS0/CS1 / CS2 O CS3/CS4/CS5 BHEN/BLEN O WAIT I Direct Memory Access Controller DMA0REQ I DMA1REQ DMA2REQ DMA0ACK O DMA1ACK DMA2ACK Inter-Integrated Circuit Controller SCL I/O SDA I/O Enhanced Serial ...
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Table 2. Signal Descriptions (Continued) Signal Mnemonic I/O MISO I/O UART Controllers TXD0/TXD1 O RXD0/RXD1 I CTS0/CTS1 I DE0/DE1 O General-Purpose Timers T0OUT/T0OUT O T1OUT/T1OUT T2OUT/T2OUT T0IN/T0IN1/T0IN2 I /T1IN/T2IN Pulse-Width Modulator for Motor Control PWMH0/PWMH1/ O PWMH2 PWML0/PWML1/ ...
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Table 2. Signal Descriptions (Continued) Signal Mnemonic I/O CINP I CINN I COMPOUT O OPINP I OPINN I OPOUT O Oscillators XIN I XOUT O On-Chip Debugger DBG I/O Caution: Reset RESET I/O Power Supply VDD I AVDD I VSS ...
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Pin Characteristics Table 3 provides information on the characteristics of each pin available on the ZNEO products. Data in Table 3. Pin Characteristics of ZNEO Symbol Reset Mnemonic Direction Direction AVDD N/A N/A AVSS N/A N/A DBG I/O I PA[7:0] ...
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Table 3. Pin Characteristics of ZNEO (Continued) Symbol Reset Mnemonic Direction Direction XIN I I XOUT O O Note: X represents integers 0, 1,... to indicate multiple pins with symbol mnemonics which differ only by an integer. PS022008-0810 Internal Active ...
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PS022008-0810 ZNEO Z16F Series Product Specification 18 Signal and Pin Descriptions ...
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Address Space The ZNEO CPU has a unique architecture with a single, unified 24-bit address space. It supports up to four memory areas: • Internal non-volatile memory (Flash, EEPROM, EPROM, or ROM). • Internal RAM. • Internal I/O memory (internal ...
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Internal I/O Memory External Memory Internal RAM External Memory Internal Non-Volatile Memory To determine the amount of internal RAM and internal non-volatile memory available for the specific device, see Internal Non-Volatile Memory Internal non-volatile memory contains executable program code, constants, ...
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... CPU Control Registers Some registers are reserved I/O memory for the ZNEO CPU control. These ZNEO CPU control registers are listed in the operation of the ZNEO CPU control registers, refer to ZNEO CPU User Manual (UM0188), available for download at www.zilog.com. PS022008-0810 Description Option bits ...
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Table 5. ZNEO CPU Control Registers Address (Hex) FF_E004-FF_E007 FF_E00C-FF_E00F FF_E010 FF_E012 External Memory Many ZNEO CPU products support external data and address buses for connecting to additional external memories and/or memory-mapped peripherals. The external addresses are used for storing ...
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Bus Widths The ZNEO CPU accesses 8-bit or 16-bit memories. The data buses of the internal non-volatile memory and internal RAM are 16-bit wide. The internal peripherals are a mix of 8-bit and 16-bit peripherals. The external memory bus ...
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PS022008-0810 ZNEO Z16F Series Product Specification 24 Address Space ...
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Peripheral Address Map Table 6 provides the address map for the peripheral space of the ZNEO products. Not all devices and package styles in the ZNEO Z16F Series support all peripherals or all GPIO ports. Registers for unimplemented peripherals are ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description IRQ2 Enable Low Bit FF_E03B Reserved FF_E03C-FF_E03F Watchdog Timer Base Address = FF_E040 Reserved FF_E040-FF_E041 Watchdog Timer Reload FF_E042 High Byte Watchdog Timer Reload FF_E043 Low Byte Reserved FF_E044-FF_E04F ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Chip Select 5 Control High FF_E07C Chip Select 5 Control Low FF_E07D Reserved FF_E07E-FF_E07F On Chip Debugger = FF_E080 Debug Receive Data FF_E080 Debug Transmit Data FF_E081 Debug Baud ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Port A Reserved FF_E10D Port A Irq Mux FF_E10E Port A Irq Edge FF_E10F GPIO Port B Base Address = FF_E110 Port B Input Data FF_E110 Port B Output ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Port D High Drive Enable FF_E133 Port D Alternate Function High FF_E134 Port D Alternate Function Low FF_E135 Port D Output Control FF_E136 Port D Pull-Up Enable FF_E137 Port ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Port G Output Data FF_E161 Port G Data Direction FF_E162 Port G High Drive Enable FF_E163 Reserved FF_E164 Port G Alternate Function Low FF_E165 Port G Output Control FF_E166 ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Port J Reserved FF_E189-FF_E18F GPIO Port K Base Address = FF_E190 Port K Input Data FF_E190 Port K Output Data FF_E191 Port K Data Direction FF_E192 Port K High ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description LIN-UART1 Mode Select and FF_E214 Status LIN-UART1 Address Compare FF_E215 Register LIN-UART1 Baud Rate High Byte FF_E216 LIN-UART1 Baud Rate Low Byte FF_E217 Reserved FF_E218-FF_E23F Base ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Timer 0 PWM Low Byte FF_E305 Timer 0 Control 0 FF_E306 Timer 0 Control 1 FF_E307 Timer 1 (General-Purpose Timer) Base Address = FF_E310 Timer 1 High Byte FF_E310 ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description Current-Sense Sample and Hold FF_E38A Control 0 Current-Sense Sample and Hold FF_E38B Control 1 Reserved FF_E38C-FF_E38B PWM High Byte FF_E38C PWM Low Byte FF_E38D PWM Reload High Byte FF_E38E ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description DMA0 Request Select FF_E400 DMA1 Request Select FF_E401 DMA2 Request Select FF_E402 DMA3 Request Select FF_E403 Reserved FF_E404-F DMA Channel 0 Base Address = FF_E410 DMA0 Control0 FF_E410 DMA0 ...
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Table 6. Register File Address Map (Continued) Address (Hex) Register Description DMA1 Source Address Upper FF_E429 DMA1 Source Address High FF_E42A DMA1 Source Address Low FF_E42B Reserved FF_E42C DMA1 List Address Upper FF_E42D DMA1 List Address High FF_E42E DMA1 List ...
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... Comparator and Op-Amp Control FF_E510 Reserved FF_E511 ADC Sample Timer Capture High FF_E512 ADC Sample Timer Capture Low FF_E513 Option Trim Registers Base Address = FF_FF00 Reserved for internal Zilog FF_FF00-FF_FF24 IPO Trim 1 FF_FF25 IPO Trim 2 FF_FF26 ADC Reference Voltage Trim FF_FF27 Note: XX=Undefined. ...
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PS022008-0810 ZNEO Z16F Series Product Specification 38 Peripheral Address Map ...
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External Interface The external interface allows seamless connection to external memory and/or peripherals. The configurable nature of the external interface supports connection with many different bus styles and signal formats. Bit-wise control of the address, data, and control signals means ...
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Table 7. External Interface Signals Description (Continued) External Interface Signal CS1 CS2 CS3 CS4 CS5 Chip Selects The chip selects support connection of multiple memories and peripherals to the external interface. Figure 9 select boundaries are at fixed addresses. On-chip ...
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Table 8. Example Usage of Chip Selects Chip Memory/Peripheral Select 64 KB Internal Flash CS0 8 MB External ROM or Flash CS1 128 KB External RAM CS2 External Ethernet MAC CS3 External CAN controller. Tools Compatibility Guidelines The external interface ...
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... Any external I/O that is located elsewhere is accessed using absolute addressing. The debugger memory window displays all addresses below Memory space. For details on how the ZDS II development tools use memory, refer to Zilog Developer Studio II— ZNEO User Manual (UM0171). External WAIT Pin Operation Setup of the external WAIT pin is selected by the GPIO alternate function ...
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CSxWAIT[3:0] field and the PRxWAIT[1:0] field as shown in the Select Control Registers number of system clock cycles. A maximum of 31 Waits states are inserted. An example of Wait state operation is illustrated in has been ...
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External Interface Control Register Definitions The following section describes the various control registers. External Interface Control Register The external interface control register enables the interface and sets the internal memory size (see Table 9). Table 9. External Interface Control Register ...
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Reserved—These bits are reserved and must be programmed to zero. CSEN—Chip select enable CSx is disabled CSx is enabled POLSEx—Polarity select CSx is active Low CSx is active High CSxISA—Chip select ISA ...
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Wait states 1000 = 8 Wait states 1001 = 9 Wait states 1010 = 10 Wait states 1011 = 11 Wait states 1100 = 12 Wait states 1101 = 13 Wait states 1110 = 14 Wait states ...
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Wait states 1110 = 14 Wait states 1111 = 15 Wait states Table 13 lists the external chip select control registers Low for CS2 to CS5 (EXTCSxL). This register sets the number of Wait states for chip ...
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External Interface Timing The following sections describe the external interface timing. External Interface Write Timing - Normal Mode Figure 11 on page 49 and performing a Write operation. In generator is configured to provide 1 Wait state during Write operations. ...
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XIN T 1 ADDR[23: DATA[15: WAIT (From pin DMAACK T 13 BHEN / BLEN Figure 11. External Interface Timing for a Write Operation - Normal Mode PS022008-0810 1 Wait State from Wait ...
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External Interface Write Timing - ISA Mode Figure 12 on page 51 and performing a Write operation. In generator has been configured to provide 1 Wait state during Write operations. The external WAIT input pin is generating an additional Wait ...
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T CLK XIN T 1 ADDR[23: DATA[15: WAIT (From pin DMAACK T 13 BHEN / BLEN Figure 12. External Interface Timing for a Write Operation - ISA Mode PS022008-0810 1 Wait State ...
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External Interface Read Timing - Normal Mode Figure 13 on page 53 and performing a Read operation in NORMAL mode. In the Wait state generator has been configured to provide 2 Wait states during Read operations. For proper data hold ...
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XIN T 1 ADDR[23:0] DATA[15: WAIT (From pin DMAACK T 13 BHEN / BLEN Figure 13. External Interface Timing for a Read Operation - Normal Mode PS022008-0810 1 Wait State from Wait ...
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Figure 14 and Table 16 provide timing information for the External Interface performing a Read operation in Normal mode with a post read wait state. The configuration is the same as in Figure 13, with the exception of the post ...
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External Interface Read Timing - ISA Mode Figure 15 on page 56 and performing a Read operation in ISA mode. In state generator has been configured to provide 2 Wait states during Read operations. In Figure 15 on page ...
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T CLK XIN T 1 ADDR[23:0] DATA[15: WAIT (From pin DMAACK T 13 BHEN / BLEN Figure 15. External Interface Timing for a Read Operation - ISA Mode PS022008-0810 1 Wait State from Wait ...
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PS022008-0810 ZNEO Z16F Series Product Specification 57 External Interface ...
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Reset and Stop Mode Recovery The reset controller within the ZNEO Recovery operation typical operation, the following events causes a Reset to occur: • Power-On Reset. • Voltage Brownout. • WDT time-out (when configured through the • External ...
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System Reset During a System Reset, the ZNEO Z16F Series device is held in Reset for 66 cycles of the IPO. At the beginning of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are disabled. At ...
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Power-On Reset Each device in the ZNEO Z16F Series contains an internal POR circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the ...
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POR voltage threshold (V state. When the supply voltage exceeds the V through a full System Reset sequence, as described in the section page 60. Following Power-on reset, the POR status bit in the reset source register ...
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External Pin Reset The input-only RESET pin has a schmitt-triggered input, an internal pull-up, an analog filter and a digital filter to reject noise. Once the RESET pin is asserted for at least four system clock cycles, the device progresses ...
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Stop Mode Recovery only affects the contents of the page 64 and Oscillator Control Register any other values in the register file, including the stack pointer, register pointer, flags, peripheral control registers, and general-purpose RAM. The ZNEO CPU fetches the ...
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Reset Status and Control Register The Reset status and Control (RSTSCR) register (see most recent RESET or Stop Mode Recovery. All status bits are updated on each RESET or Stop Mode Recovery event. following a RESET or Stop Mode Recovery ...
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PS022008-0810 Reset and Stop Mode Recovery ZNEO Z16F Series Product Specification 65 ...
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Low-Power Modes ® The ZNEO Z16F Series products contain advanced integrated power-saving features. Power management functions are divided into three categories to include CPU operating modes, peripheral power control, and programmable option bits. The highest level of power reduction is ...
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WDT’s internal RC oscillator continues to operate. • If enabled, the WDT continues to operate. • All other on-chip peripherals continue to operate. The ZNEO CPU is brought out of HALT mode by any of the following operations: • ...
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General-Purpose Input/Output ® The ZNEO Z16F Series products contain general-purpose input/output (GPIO) pins arranged as Ports A–K. Each port contains control and data registers. The GPIO control registers are used to determine data direction, open-drain, output drive current, and alternate ...
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Port Output Control Port Output Data Register Data D Q Bus System Clock Port Data Direction Figure 17. GPIO Port Pin Block Diagram GPIO Alternate Functions Many GPIO port pins are used for GPIO and to provide access to the ...
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Table 24. Port Alternate Function Mapping Port Pin Alternate Function 1 PA0 T0IN / T0OUT Port A PA1 T0OUT PA2 DE0 PA3 CTS0 PA4 RXD0 PA5 TXD0 PA6 SCL PA7 SDA PB0/T0IN0 ANA0 Port B PB1/T0IN1 ANA1 PB2/T0IN2 ANA2 PB3 ...
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Table 24. Port Alternate Function Mapping (Continued) Port Pin Alternate Function 1 PD0 PWMH1 Port D PD1 PWML1 PD2 PWMH2 PD3 DE1 PD4 RXD1 PD5 TXD1 PD6 CTS1 PD7 PWML2 PE0 Port E PE1 PE2 PE3 PE4 PE5 PE6 PE7 ...
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Table 24. Port Alternate Function Mapping (Continued) Port Pin Alternate Function 1 PG0 ADDR[8] Port G PG1 ADDR[9] PG2 ADDR[10] PG3 ADDR[11] PG4 ADDR[12] PG5 ADDR[13] PG6 ADDR[14] PG7 ADDR[15] PH0 ANA8 Port H PH1 ANA9 PH2 ANA10 PH3 ANA11/CPINP ...
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GPIO Interrupts Many of the GPIO port pins are used as interrupt sources. Some port pins are configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other port pin interrupts ...
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POUT[7:0]—Port Output Data These bits contain the data to be driven out from the port pins. The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. ...
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Port A-K High Drive Enable Registers Setting the bits in the Port A-K high drive enable registers (see the specified port pins for high current output drive operation. The Port A-K high drive enable registers affect the pins directly, and ...
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Table 30. Port A-K Alternate Function Low Registers (PxAFL BITS AFL[7] AFL[6] FIELD 0 0 RESET R/W R/W R/W FF_E105, FF_E115, FF_E125, FF_E135, FF_E155, FF_E165, FF_E175, FF_E195 ADDR Table 31. Alternate Function Enabling AFH[x] AFL[ ...
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The drains are enabled for any output mode. The drain of the associated pin is disabled (open-drain mode). Port A-K Pull-Up Enable Registers Setting the bits in the Port A-K pull-up enable registers (see internal resistive ...
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PSMRE[7:0]—Port Stop Mode Recovery Source Enabled The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin during STOP mode do not initiate Stop Mode Recovery. The port pin is configured ...
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PAIMUX[7:0]—Port A/D Interrupt Source Select Port Ax as interrupt source. Select Port Dx as interrupt source. Port A Irq Edge Register The Port Irq Edge register (see pin interrupt sources. Table 37. Port A Irq Edge ...
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... The ZNEO Z16F Series supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. For more information on interrupt servicing by the ZNEO CPU, refer to the ZNEO CPU User Manual available for download at www.zilog.com. PS022008-0810 ® Z16F Series products prioritize interrupt requests ...
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Interrupt Vector Listing Table 39 lists all the interrupts available in order of priority. Table 39. Interrupt Vectors in Order of Priority Priority Program Memory Vector Address Highest 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H ...
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Table 39. Interrupt Vectors in Order of Priority (Continued) Priority Program Memory Vector Address 0060H 0064H 0068H Lowest 006CH The most significant byte (MSB) of the four byte interrupt vector is not used. The vector is stored in the three ...
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Architecture Figure 18 displays a block diagram of the interrupt controller. Port Interrupts Internal Interrupts Figure 18. Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit in the flag register globally enables or disables interrupts. This ...
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Reset • Execution of a • All System Exceptions Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is ...
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System Exception Status Registers When a System Exception occurs the system exception status registers is read to determine which system exception occurred. These registers are read individually or read as a 16-bit quantity. Table 41. System Exception Register High (SYSEXCPH) ...
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Reserved—These bits are reserved WDTOSC—WDT Oscillator Fail If this bit WDT oscillator fail exception occurred. Writing 1 to this bit clears PRIOSC—Primary Oscillator Fail If this bit primary oscillator fail exception ...
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Table 44. Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register (IRQ0SET) BITS 7 6 T2I T1I FIELD 0 0 RESET R/W1C R/W1C R/W ADDR T2I T1I FIELD 0 0 RESET W W R/W ADDR Note: IRQ0SET at ...
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I2CI—I2C Interrupt Request interrupt request is pending for the I2C. interrupt request from the I2C is awaiting service. Writing 1 to this bit Resets SPII—SPI Interrupt Request interrupt ...
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Here x indicates the specific GPIO port pin number (0 through 7). PAD7I and PAD0I have interrupt sources other than Port A and Port D as selected by the Port A Irq Mux registers. PAD7I is configured to provide the ...
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U1RXI—UART 1 Receiver Interrupt Request interrupt request is pending for the UART 1 receiver. interrupt request from the UART 1 receiver is awaiting service. Writing 1 to this bit Resets U1TXI—UART ...
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Table 48. IRQ0 Enable High Bit Register (IRQ0ENH) BITS 7 6 T2ENH T1ENH FIELD 0 0 RESET R/W R/W R/W ADDR T2ENH — Timer 2 Interrupt Request Enable High Bit T1ENH — Timer 0 Interrupt Request Enable High Bit T0ENH ...
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IRQ1 Enable High and Low Bit Registers The IRQ1 enable high and low bit registers (see encoded enabling for interrupts in the interrupt request 1 register. Priority is generated by setting bits in each register. Table 50. IRQ1 Enable and ...
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IRQ2 Enable High and Low Bit Registers The IRQ2 enable high and low bit registers (see encoded enabling for interrupts in the interrupt request 2 register. Priority is generated by setting bits in each register. Table 53. IRQ2 Enable and ...
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Table 55. IRQ2 Enable Low Bit Register (IRQ2ENL) BITS 7 6 PWMTENL U1RENL U1TENL PWMFENL FIELD 0 0 RESET R/W R/W R/W ADDR PWMTENL—PWM Timer Interrupt Request Enable Low Bit U1RENL—UART 1 Receive Interrupt Request Enable Low Bit U1TENL—UART 1 ...
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PS022008-0810 ZNEO Z16F Series Product Specification 95 Interrupt Controller ...
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Timers ® The ZNEO Z16F Series contains three 16-bit reloadable timers used for timing, event counting, or generation of pulse width modulated (PWM) signals. Features The timers include the following features: • 16-bit reload counter. • Programmable prescaler with values ...
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Operation The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initialized to 0001H reload high and low byte registers, then resets to continues depending on the mode. Minimum time-out delay (1 system clock) is set by ...
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Set the initial output level (High or Low) using the TPOL bit for the timer output alternate function. – Set the INTERRUPT mode. 2. Write to the timer high and low byte registers to set the starting count value. ...
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Write to the timer high and low byte registers to set the starting count value. 3. Write to the timer reload high and low byte registers to set the reload value. 4. Enable the timer interrupt, if required, and ...
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Continuous Mode Time-Out Period ( initial starting value other than registers, use the ONE-SHOT mode equation to determine the first timeout period. COUNTER and COMPARATOR COUNTER Modes In COUNTER mode, the timer counts input transitions from a GPIO ...
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Write to the timer reload high and low byte registers to set the starting count value. This affects only the first pass in the COUNTER modes. After the first timer Reload, counting always begins at the reset value of ...
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Write to the timer high and low byte registers to set the starting count value (typically ). The starting count value only affects the first pass in PWM mode. After the 0001H first timer reset in PWM mode, counting ...
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If the timer output alternate function is enabled, the timer output pin changes state (from Low to High or High to Low) at timer Reload. The initial value is determined by the TPOL bit. CAPTURE Mode When the timer is ...
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Configure the timer interrupt to be generated at the input capture event, the reload event or both by setting 2. Write to the timer reload high and low byte registers to set the starting count value (typically 0001H 3. ...
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Write to the timer control 1 register to enable the timer and initiate counting. The compare time is calculated by the following equation (Start Value = 1): Compare Mode Time (s) GATED Mode In GATED mode, the timer counts ...
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Reading Timer Count Values The current count value in the timer is read while counting (enabled). This has no effect on timer operation. Normally, the count must be read with one 16-bit operation. However, 8 bit reads are done ...
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Table 57. Timer 0-2 Low Byte Register (TXL) BITS 7 6 FIELD RESET R/W ADDR TH and TL—Timer High and Low Bytes These two bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. Timer X Reload High and Low ...
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Timer 0-2 PWM High and Low Byte Registers The timer 0-2 PWM high and low byte (TxPWMH and TxPWML) registers Table 61 on page 108) define PWM operations. These registers also store the timer counter values for the CAPTURE modes. ...
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Table 62. Timer 0-2 Control 0 Register (TxCTL0) BITS 7 6 TMODE[3] TICONFIG FIELD 0 RESET R/W R/W ADDR Bit Position Value (H) Description [7] Timer Mode High Bit TMODE[3] This bit along with TMODE[2:0] field in T 0CTL1 register ...
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Bit Position Value (H) Description [3:1] PWM Delay Value PWMD This field is a programmable delay to control the number of additional system clock cycles following a PWM or Reload compare before the timer output or the timer output complement ...
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Bit Position Value (H) Description [6] Timer Input/Output Polarity TPOL This bit nction of the cur rent operating mode of the timer. It determines the polarity of the input and/or output signal. When the timer is disabled, ...
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Bit Position Value (H) Description PWM DUAL OUTPUT mode — If enabled, the timer output is set=TPOL after PWM match and set = TPOL after Reload. If enabled the timer output complement takes on the opposite value of the timer ...
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PS022008-0810 ZNEO Z16F Series Product Specification 113 Timers ...
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Multi-Channel PWM Timer ® The ZNEO Z16F Series includes a Multi-Channel PWM optimized for motor control applications. The PWM includes the following features: • Six independent PWM outputs or three complementary PWM output pairs. • Programmable deadband insertion for complementary ...
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Counter with Prescaler PWM Deadband Data Bus System Clock Operation PWM Option Bits To protect the configuration of critical PWM parameters, settings to enable output channels and the default off-state are maintained as user option bits. These values are ...
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PWM Output Polarity and Off-State The default off-state and polarity of the PWM outputs are controlled by the option bits PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM high-side outputs PWMH0, PWMH1, and PWMH2. The ...
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The programmed duty-cycle (PWMDC) and the programmed deadband time (PWMDB) determine the active time of a PWM output. The following sections describe the PWM TIMER modes and the registers controlling the duty-cycle and deadband time. PWMxH No Dead Band ...
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EDGE-ALIGNED Mode In EDGE-ALINGED PWM mode, a 12-bit up counter creates the PWM period with a minimum resolution equal to the PWM clock source period. The counter counts up to the Reload value, resets to Edge-Aligned PWM Mode Period CENTER-ALINGED ...
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PWM timer count reaches the programmed duty cycle. The low-side PWM value starts in the off-state and transits to the on-state as the PWM timer count reaches the value in the associated duty ...
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The pulse width filter value is calculated as: roundup PWMMPF where T minPulseOut Synchronization ...
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The fault inputs are individually enabled through the PWM fault control register fault condition is detected and the source is enabled, the fault interrupt is generated. The Fault Status Register (PWMFSTAT) interrupt. When a fault is detected and ...
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PWM High and Low Byte Registers The PWM high and low byte (PWMH and PWML) registers (see contain the current 12-bit PWM count value. Reads from PWMH stores the value in PWML to a temporary holding register. A read from ...
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Edge-Aligned PWM Mode Period Center-Aligned PWM Mode Period Table 66. PWM Reload High Byte Register (PWMRH) BITS 7 6 Reserved FIELD RESET R/W R/W ADDR Table 67. PWM Reload Low Byte Register (PWMRL) BITS 7 6 FIELD RESET R/W ADDR ...
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PWM Duty Cycle Writing a negative value (DUTYH[ forces the PWM to be OFF for the full PWM period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM for the ...
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Table 70. PWM Control 0 Register (PWMCTL0) BITS 7 6 PWMOFF OUTCTL FIELD 0 0 RESET R/W R/W R/W ADDR Bit Position Value (H) Description [7] Place PWM outputs in off-state PWMOFF Disable modulator control of PWM pins. Outputs are ...
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Bit Position Value (H) Description [0] PWM Enable PWMEN PWM is disabled and enabled PWM o utput pins are forced to default off- 0 state. PWM master counter is stopped. 1 PWM is enabled and PWM output pins are enabled ...
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PWM Control 1 Register The PWM Control 1 (PWMCTL1) register controls portions of PWM operation. Table 71. PWM Control 1 Register (PWMCTL1) BITS 7 6 RLFREQ[1:0] FIELD 00 RESET R/W R/W ADDR Bit Position Value (H) Description [7:6] Reload Event ...
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PWM Deadband Register The PWM deadband (PWMDB) register (see value. The deadband value determines the number of PWM input cycles to use for the deadband time for complementary PWM output pairs. When counting PWM input cycles, the PWM input signal ...
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PWM Fault Mask Register The PWM fault mask register, enables individual fault sources. When an input is asserted, PWM behavior is determined by the The PWM Fault Mask (PWMF) the Comparator 0-3 outputs generate PWM faults and the associated fault ...
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PWM Fault Status Register The PWM fault status (PWMFSTAT) register provides status of fault inputs and timer reload. The fault flags indicate the fault source, which is active fault source is masked, the flag in this register is ...
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PWM Fault Control Register The PWM fault control (PWMFCTL) register (see recovers from a fault condition. Settings in this register select automatic or software controlled PWM restart. Table 76. PWM Fault Control Register (PWMFCTL) BITS 7 6 Reserved DBGRST CMP1INT ...
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Bit Position Value (H) Description [2] Comparator 0 Restart CMP0RST Automatic recovery. PWM resumes control of outputs when all fault sources 0 have deasstered. oftware Controlled Recovery. PWM resumes control of outputs only after S 1 all fault sources have ...
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Bit Position Value (H) Description [5:0] Sample PWM pins IN2L/IN2H/ Low-level signal was read on the pins. IN1L/IN1H/ A High-level signal was read on the pins. 1 IN0L/IN0H PWM Output Control Register The PWM output control (PWMOUT) register ...
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Disabling the HEN, LEN, NHEN, and NLEN bits allows software control of the input sample/hold by writing the SHPOL bit. . Table 79. Current-Sense Sample and Hold Control Register (CSSHR0 and CSSHR1) BITS 7 6 ...
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LIN-UART The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LIN- UART full-duplex communication channel capable of handling asynchronous data transfers in standard UART applications as well as providing LIN protocol support. Features of the LIN-UART include: • 8-bit asynchronous ...
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Architecture The LIN-UART consists of three primary functional blocks: transmitter, receiver, and BRG. The LIN-UART’s transmitter and receiver function independently but use the same baud rate and data format. The basic UART operation is enhanced by the noise filter and ...
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Operation Data Format for Standard UART Modes The LIN-UART always transmits and receives data in an 8-bit data format with the first bit being least-significant bit. An even- or odd-parity bit or multiprocessor address/data bit is optionally added to the ...
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If MULTIPROCESSOR mode is required, write to the LIN-UART control 1 register to enable MULTIPROCESSOR (9-bit) mode functions. (a) Set the MULTIPROCESSOR mode select ( mode. 4. Write to the LIN-UART control 0 register to: (a) Set the transmit ...
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If MULTIPROCESSOR mode is required, write to the LIN-UART control 1 register to enable MULTIPROCESSOR (9-bit) mode functions. (a) Set the MULTIPROCESSOR mode select (MPEN) to enable MULTIPROCESSOR mode. 6. Write to the LIN-UART Control 0 register to: (a) ...
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Write to the LIN-UART Control 0 register to: (a) Set the receive enable bit (REN) to enable the LIN-UART for data reception (b) Enable parity, if MULTIPROCESSOR mode is not enabled, and select either even or odd parity. 5. ...
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Write to the LIN-UART control 0 register to: (a) Set the receive enable bit ( (b) Enable parity, if MULTIPROCESSOR mode is not enabled, and select either even- or odd-parity. 9. Execute an EI The LIN-UART is now configured ...
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DE 0 Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 26. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) The DE to Start bit setup time is calculated as follows: 1 ...
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The character format is given below: Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 27. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format In MULTIPROCESSOR (9-bit) mode, the MULTIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers ...
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If the new frame’s address matches the LIN-UART’s, then the data in the new frame is processed. The second scheme is enabled by setting address into the LIN-UART address compare register. This mode introduces more hardware control, interrupting ...
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In LIN mode, the interrupts defined for normal UART operation still apply with the following changes: • Parity error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE) bit. The PLE bit indicates that receive data ...
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In addition to the LMST, LSLV, and ABEN bits in the LIN control register, a LinState[1:0] field exists that defines the current state of the LIN logic. This field is initially set by the software. In the LIN SLAVE mode, ...
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If the CPU is in HALT or OPERATIONAL mode, the LIN-UART (if enabled) times the duration of the Wake-up and provides an interrupt following the end of the break sequence if the duration is 4 bit times. The total ...
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Transmitter Interrupts The transmitter generates a single interrupt when the transmit data register empty bit ( ) is set to 1. This indicates that the transmitter is ready to accept new data for TDRE transmission. The TDRE interrupt occurs when ...
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OE bit. In this case software must write Break state. LIN-UART Data and Error Handling Procedure Figure 28 displays the recommended procedure for use in LIN-UART receiver interrupt ...
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BRG to function as an additional counter if the LIN-UART receiver functionality is not employed. The transmitter is enabled in this mode. LIN-UART DMA Interface The DMA engine is configured to move UART transmit and/or receive data. ...
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When configured as a general purpose timer, the BRG interrupt interval is calculated using the following equation: UART BRG Interrupt Interval (s) Noise Filter A noise filter circuit is included, which filters noise on a digital input signal such as ...
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Figure 29. Noise Filter System Block Diagram Operation Figure 30 on page 152 displays the operation of the noise filter with and without noise. The noise filter in this example is a 2-bit up/down counter, which saturates at bit counter ...
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Sample Clock Input RxD (ideal) Noise Filter ...
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LIN-UART Transmit Data Register Data bytes written to the LIN-UART transmit data register (see the TXD pin. The Write-only LIN-UART transmit data register shares a Register File address with the Read-only LIN-UART Receive Data register. Table 80. LIN-UART Transmit Data ...
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LIN-UART Status 0 Register The LIN-UART Status 0 register identifies the current LIN-UART operating configuration and status. Table 82 Table 83 on page 155 describes the Status 0 register for LIN mode. Table 82. LIN-UART Status 0 Register – Standard ...
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No break occurred. break occurred. TDRE—Transmitter Data Register Empty This bit indicates that the transmit data register is empty and ready for additional data. Writing to the transmit data register resets this bit. ...
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OE—Receive Data and Autobaud Overrun Error This bit is set just as in normal UART operation if a receive data overrun error occurs. This bit is also set during LIN slave autobaud if the BRG counter overflows before the end ...
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LIN-UART Mode Select and Status Register This register contains mode select and status bits. Table 84. LIN-UART Mode Select and Status Register (UxMDSTAT BITS MSEL FIELD 0 0 RESET R/W R/W R/W ADDR MSEL—Mode Select This R/W ...
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The current byte is not the first data byte of a new frame. The current byte is the first data byte of a new frame. MPRX—Multiprocessor Receive Returns the value of the last multiprocessor bit received. ...
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LIN-UART Control 0 Register The LIN-UART Control 0 register (see LIN-UART’s transmit and receive operations. Table 85. LIN-UART Control 0 Register (UxCTL0 BITS TEN REN FIELD 0 0 RESET R/W R/W R/W ADDR TEN—Transmit Enable This bit enables ...
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SBRK bit is deasserted by hardware when the Break is completed. The duration of the Break is determined by the TxBreakLength field of the LIN control register. One or two Stop bits are ...
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The LIN-UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the address compare register. MPEN—MULTIPROCESSOR (9-bit) Enable This bit is used to enable ...
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Noise Filter Control Register (LIN-UART Control1 Register with MSEL = 001b). When = MSEL 001b Table 87. Noise Filter Control Register (UxCTL1 with MSEL = 001b BITS NFEN FIELD 0 0 RESET R/W R/W R/W ADDR NFEN—Noise Filter ...
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LMST—LIN Master Mode LIN Master mode not selected. LIN Master mode selected (if LSLV—LIN Slave Mode LIN Slave mode not selected. LIN Slave mode selected (if ABEN—Autobaud Enable Autobaud not ...
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LIN-UART Address Compare Register The LIN-UART address compare register stores the multi-node network address of the LIN-UART. When the address bytes are compared to the value stored in the address compare register. Receive interrupts and RDA Table 89. LIN-UART Address ...
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Table 91. LIN-UART Baud Rate Low Byte Register (UxBRL) BITS 7 6 FIELD RESET R/W ADDR The LIN-UART data rate is calculated using the following equation for standard UART modes. For LIN protocol, the baud rate registers must be programmed ...
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The baud rate error relative to the appropriate baud rate is calculated using the following equation: UART Baud Rate Error (%) For reliable communication, the LIN-UART baud rate error must never exceed 5 percent. Table 92 on page 167 provides ...
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Table 92. LIN-UART Baud Rates 20.0 MHz System Clock Desired BRG Actual Rate Error Rate Divisor (kHz) (Decimal) (kHz) 1250.0 1 1250.0 625.0 2 625.0 250.0 5 250.0 115.2 11 113.64 57.6 22 56.82 38.4 33 37.88 19.2 65 19.23 ...
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Table 92. LIN-UART Baud Rates (Continued) 5.5296 MHz System Clock Desired BRG Rate Divisor Actual Rate Error (kHz) (Decimal) (kHz) 1250.0 N/A N/A 625.0 N/A N/A 250.0 1 345.6 115.2 3 115.2 57.6 6 57.6 38.4 9 38.4 19.2 18 ...
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Table 92. LIN-UART Baud Rates (Continued) 1.8432 MHz System Clock Desired BRG Actual Rate Error Rate Divisor (kHz) (Decimal) (kHz) 1250.0 N/A N/A 625.0 N/A N/A 250.0 N/A N/A 115.2 1 115.2 57.6 2 57.6 38.4 3 38.4 19.2 6 ...
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PS022008-0810 ZNEO Z16F Series Product Specification 170 LIN-UART ...
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... UART. Communication is half-duplex, which means that simultaneous data transmission and reception is not allowed. PS022008-0810 RxD Infrared TxD Encoder/Decoder Baud Rate (Endec) Clock ZNEO Z16F Series Product Specification ® Zilog ZHX1810 RXD RXD TXD TXD Infrared Transceiver Infrared Encoder/Decoder 171 ...
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The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to ...
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Receiving IrDA Data Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to ...
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If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, ...
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Enhanced Serial Peripheral Interface The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface) and Inter IC Sound (I The features of the ESPI include: • Full-duplex, synchronous, character-oriented communication. • Four-wire interface (SS, SCK, MOSI, MISO). • Transmit ...
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Peripheral Bus ESPI Control ESPI Status Register Register ESPI State ESPI Mode Register Register ESPI State Machine SS out SS in MISO MOSI PS022008-0810 ESPI BRH Register ESPI BRL Register Baud Generator count = 1 Transmit Data ...
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ESPI Signals The four ESPI signals are: • Master-In/Slave-Out (MISO) • Master-Out/Slave-In (MOSI) • Serial clock (SCK) • Slave select (SS) The following paragraphs describe these signals in both MASTER and SLAVE modes. The appropriate GPIO pins must be configured ...
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SSIO bit of the ESPI mode register. The SS signal is an input on slave devices and is an output on the active master device. Slave devices ignore transactions on the bus unless their slave select input ...
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Mode register: – Added SSMD field which adds support for loop back and I2S modes. – Moved SSV bit to the transmit data command register as described above. – Added slave select polarity (SSPO) to support active High and ...
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ESPIEN1, 0 bits in the control register to move the data, the transmit and receive data interrupts are disabled through the DIRQE bit of the control register. In this case error interrupts still occurs and must be handled directly by ...
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Master or Slave timing diagram as the SCK MISO and MOSI pins are directly connected between the master and the slave. SCK (CLKPOL = 0) SCK (CLKPOL = 1) MOSI Bit7 MISO Bit7 Input Sample Time ...
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SCK (CLKPOL = 0) SCK (CLKPOL = 1) MOSI MISO Input Sample Time SS Figure 36. ESPI Timing when Modes of Operation This section describes the different modes of data transfer supported by the ESPI block. The mode is selected ...
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DMA request is being serviced (set TEOF before or simultaneously with writing the last data byte). When the last bit of the last character is transmitted, the hardware will automatically deassert the SSV ...
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SCK (SSMD = 00, PHASE = 0, CLKPOL = 0, SSPO = 0) Bit0 MOSI, MISO Rx Data Register Data Register Shift Register Tx/Rx n-1 TDRE RDRF ESPI Interrupt I2S (Inter-IC Sound) Mode This mode is selected ...