C8051F335-GM Silicon Laboratories Inc, C8051F335-GM Datasheet - Page 24
C8051F335-GM
Manufacturer Part Number
C8051F335-GM
Description
IC 8051 MCU 2KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F335-GM
Program Memory Type
FLASH
Program Memory Size
2KB (2K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Data Rom Size
128 B
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1269
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C8051F330/1/2/3/4/5
1.4.
C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The
C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be
configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be config-
ured for push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be
globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See
Figure 1.11.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital sig-
nals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control
registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for the particular application.
1.5.
The C8051F330/1/2/3/4/5 Family includes an SMBus/I
baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
26
Highest
Priority
Lowest
Priority
Programmable Digital I/O and Crossbar
Serial Ports
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
CP0
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 1.11. Digital Crossbar Diagram
2
4
2
2
4
2
8
8
Rev. 1.7
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
2
C interface, a full-duplex UART with enhanced
8
8
PnMDIN Registers
PnMDOUT,
Cells
Cells
I/O
I/O
P0
P1
P0.0
P0.7
P1.0
P1.7
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