MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 101

• Manufacturer Part Number: MC68HC908QY1VDTE
• Description: IC MCU 1.5K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908QY1VDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-TSSOP
• Processor Series: HC08Q
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading
address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
Freescale Semiconductor
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Address: $0005
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
DDRB
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
port B I/O logic.
Reset:
Read:
Write:
Bit
0
1
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
DDRB7
Bit 7
PTB
X
0
Bit
X
(1)
Figure 12-6. Data Direction Register B (DDRB)
Table 12-2
DDRB6
Input, Hi-Z
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
I/O Pin
Output
RESET
Mode
Table 12-2. Port B Pin Functions
Figure 12-7. Port B I/O Circuit
DDRB5
(2)
summarizes the operation of the port B pins.
5
0
Accesses to DDRB
DDRB7–DDRB0
DDRB7–DDRB0
DDRBx
DDRB4
NOTE
PTBx
Read/Write
4
0
DDRB3
3
0
Figure 12-7
DDRB2
Read
2
0
Pin
Pin
PTBPUEx
Accesses to PTB
DDRB1
PTB7–PTB0
PTB7–PTB0
1
0
shows the
Write
30 k
DDRB0
Bit 0
PTBx
0
(3)
Port B
101