MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 74

IC MCU 8K FLASH 8MHZ 32-DIP

MC68HC908JL8CSPE

Manufacturer Part Number
MC68HC908JL8CSPE
Description
IC MCU 8K FLASH 8MHZ 32-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC68HC908JL8CSPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
26
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Controller Family/series
HC08
No. Of I/o's
26
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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System Integration Module (SIM)
5.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is
set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long start-up times from stop mode.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register
(BSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
74
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
ICLK
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
RST
IDB
IAB
IAB
IDB
$A6
Figure 5-16. Wait Recovery from Interrupt or Break
$A6
Figure 5-17. Wait Recovery from Internal Reset
$6E0B
$A6
$6E0B
$A6
RST
pin OR CPU interrupt OR break interrupt
$A6
$A6
Cycles
32
$6E0C
NOTE
NOTE
$01
Figure 5-18
Cycles
$00FF
32
$0B
$00FE
shows stop mode entry timing.
$6E
RST VCT H
$00FD
RST VCT L
$00FC
Freescale Semiconductor

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