R5F21262SNFP#U0 Renesas Electronics America, R5F21262SNFP#U0 Datasheet - Page 321
R5F21262SNFP#U0
Manufacturer Part Number
R5F21262SNFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21262SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.31
16.3.3
(1) I
(2) I
Explanation of symbols
S
SLA
R/W
A
DATA : Transmit / receive data
P
16.3.3.1
(a) I
(b) I
2
2
C bus format
C bus timing
Setting the FS bit in the SAR register to 0 enable communication in I
Figure 16.31 shows the I
8 bits.
2
2
: Start condition
: Slave address
: Indicates the direction of data transmit/receive
: Acknowledge
: Stop condition
C bus format (FS = 0)
C bus format (when start condition is retransmitted, FS = 0)
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
The receive device sets the SDA signal to “L”.
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
SDA
SCL
Sep 26, 2008
S
S
1
1
I
2
C bus Interface Mode
S
I
I
2
2
C bus Format and Bus Timing
C bus Format
SLA
SLA
7
7
1 to 7
SLA
1
1
Page 302 of 453
R/W
R/W
8
1
1
R/W
2
C bus Format and Bus Timing. The 1st frame following the start condition consists of
A
A
1
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
9
A
S
1
A/A
1 to 7
1
SLA
7
P
1
DATA
2
1
C bus format.
Transfer bit count (n = 1 to 8)
Transfer frame count (m = from 1)
8
16. Clock Synchronous Serial Interface
R/W
1
9
A
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
A
1
P
DATA
n2
m2
A/A
1
P
1
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