MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 64

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
Mask Option Register (MOR)
LEVEL — IRQ Edge Sensitivity
LSBF — SIOP Least Significant Bit First
SPR0 and SPR1 — SIOP Clock Rate
SWAIT — STOP Instruction Mode
SECURE — Security State
PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
64
difficult for unauthorized users.
If the LEVEL bit is clear, the IRQ/V
to the IRQ/V
the input signal and the logic low level of the input signal on the IRQ/V
If the LSBF bit is set, the serial data to and from the SIOP will be transferred least significant bit first.
If the LSBF bit is clear, the serial data to and from the SIOP will be transferred most significant bit first.
The SPR0 and SPR1 bits determine the clock rate used to transfer the serial data to and from the
SIOP. The various clock rates available are given in
Setting the SWAIT bit will prevent the STOP instruction from stopping the on-board oscillator. Clearing
the SWAIT bit will permit the STOP instruction to stop the on-board oscillator and place the MCU in
stop mode. Executing the STOP instruction when SWAIT is set will place the MCU in halt mode. See
3.4.1 STOP Instruction
If SECURE bit is set, the EPROM is locked.
If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The interrupt sensitivity will be selected
via the LEVEL bit in the same way as the IRQ pin.
The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.
PP
pin. If the LEVEL bit is set, the IRQ/V
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
for additional information.
(1)
SPR1
0
0
1
1
Table 11-1. SIOP Clock Rate
PP
pin will only be sensitive to the falling edge of the signal applied
SPR0
0
1
0
1
NOTE
SIOP Master Clock
PP
Table
pin will be sensitive to both the falling edge of
f
f
f
osc
osc
osc
f
osc
11-1.
÷ 64
÷ 32
÷ 16
÷ 8
PP
pin.
Freescale Semiconductor