R5F21265SDFP#U0 Renesas Electronics America, R5F21265SDFP#U0 Datasheet - Page 246
R5F21265SDFP#U0
Manufacturer Part Number
R5F21265SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21265SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21265SDFP#U0R5F21265SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 14.64
Figure 14.65
Timer RE Hour Data Register
Timer RE Day of Week Data Register
b7 b6 b5 b4
b7 b6 b5 b4
Sep 26, 2008
b3 b2
b3 b2
b1 b0
TREHR Register in Real-Time Clock Mode
TREWK Register in Real-Time Clock Mode
b1 b0
Bit Symbol
Bit Symbol
Symbol
TREHR
TREWK
(b6-b3)
HR00
HR01
HR02
HR03
HR10
HR11
Symbol
BSY
(b6)
WK0
WK2
WK1
BSY
—
Page 227 of 453
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1st digit of hour count bits
2nd digit of hour count bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
Day of w eek count bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
Address
Bit Name
011Ah
Address
Bit Name
011Bh
Count 0 to 9 every hour. When the
digit moves up, 1 is added to the 2nd
digit of hour.
Count 0 to 1 w hen the H12_H24 bit is
set to 0 (12-hour mode).
Count 0 to 2 w hen the H12_H24 bit is
set to 1 (24-hour mode).
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
b2 b1 b0
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
1 1 1 : Do not set
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
After Reset
Function
00h
After Reset
Function
00h
0 to 9
(BCD
code)
0 to 2
(BCD
code)
Setting
Range
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
—
—
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