R5F21265SDFP#U0 Renesas Electronics America, R5F21265SDFP#U0 Datasheet - Page 355
R5F21265SDFP#U0
Manufacturer Part Number
R5F21265SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21265SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21265SDFP#U0R5F21265SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
17.5
Table 17.2
Synch Break detection
Synch Break generation
completed
Synch Field
measurement completed
Bus collision detection
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 17.2 lists the Interrupt Requests of Hardware LIN.
Interrupt Request
Interrupt Requests
Sep 26, 2008
Interrupt Requests of Hardware LIN
Page 336 of 453
Status Flag
BCDCT
SBDCT
SFDCT
Generated when the RXD0 input and TXD0 output values
Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
differed at data latch timing while UART0 is enabled for
transmission.
Cause of Interrupt
17. Hardware LIN
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