R5F21265SDFP#U0 Renesas Electronics America, R5F21265SDFP#U0 Datasheet - Page 375
R5F21265SDFP#U0
Manufacturer Part Number
R5F21265SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21265SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21265SDFP#U0R5F21265SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 19.4
19.3.2
Option Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
3.
4.
5.
6.
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode.
Figure 19.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
If the block including the OFS register is erased, FFh is set to the OFS register.
For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are
reset).
The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the
LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).
For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are
reset).
Sep 26, 2008
1
ROM Code Protect Function
OFS Register
1
Bit Symbol
CSPROINI
ROMCP1
LVD0ON
LVD1ON
WDTON
ROMCR
Symbol
OFS
(b1)
(b4)
Page 356 of 453
—
—
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bit
Voltage detection 0
circuit start bit
Voltage detection 1
circuit start bit
Count source protect
mode after reset select
bit
(1)
Address
Bit Name
0FFFFh
(2, 4)
(5, 6)
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1.
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1.
0 : Voltage monitor 0 reset enabled after hardw are
1 : Voltage monitor 0 reset disabled after hardw are
0 : Voltage monitor 1 reset enabled after hardw are
1 : Voltage monitor 1 reset disabled after hardw are
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
reset
reset
reset
reset
When Shipping
Function
FFh
(3)
19. Flash Memory
RW
RW
RW
RW
RW
RW
RW
RW
RW
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