R5F21265SDFP#U0 Renesas Electronics America, R5F21265SDFP#U0 Datasheet - Page 455
R5F21265SDFP#U0
Manufacturer Part Number
R5F21265SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21265SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21265SDFP#U0R5F21265SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
21.3.3
21.3.3.1
21.3.3.2
21.3.3.3
21.3.3.4
21.3.3.5
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Switching procedure
Switching procedure
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
• Stop the count before switching the count source.
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
Sep 26, 2008
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
elapse after changing the clock setting before stopping fOCO40M.
(refer to Table 14.11 Timer RC Operation Clock).
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
Notes on Timer RC
Program Example
Program Example
TRC Register
Count Source Switching
Input Capture Function
TRCMR Register in PWM2 Mode
TRCSR Register
Page 436 of 453
L1:
L1:
MOV.W
JMP.B
MOV.W
MOV.B
JMP.B
MOV.B
#XXXXh, TRC
L1
TRC,DATA
#XXh, TRCSR
L1
TRCSR,DATA
;Write
;JMP.B instruction
;Read
;Write
;JMP.B instruction
;Read
21. Usage Notes
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