C8051F34A-GM Silicon Laboratories Inc, C8051F34A-GM Datasheet - Page 172
C8051F34A-GM
Manufacturer Part Number
C8051F34A-GM
Description
IC 8051 MCU 64K FLASH MEM 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheet
1.C8051F349-GQ.pdf
(276 pages)
Specifications of C8051F34A-GM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4352 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
32QFN EP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Cpu Family
C8051F34x
Device Core Size
8b
Frequency (max)
48MHz
Total Internal Ram Size
4.25KB
# I/os (max)
25
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1350-5
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
16.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 16.11 through USB Register Definition 16.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 16.14 through USB Register Definition 16.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to ‘1’. The USB0 interrupt is enabled via
the EIE1 SFR (see
Important Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.
172
Bits7-0:
Bits7-3:
Bits2-0:
Bit7
Bit7
R
R
-
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low
Frame Number Low
This register contains bits7-0 of the last received frame number.
Unused. Read = 0. Write = don’t care.
Frame Number High Byte
This register contains bits10-8 of the last received frame number.
Bit6
Bit6
R
R
-
Section “9.3. Interrupt Handler” on page 88
Bit5
Bit5
R
R
-
Frame Number Low
Bit4
Bit4
R
R
-
Rev. 1.3
Bit3
Bit3
R
R
-
Bit2
Bit2
R
R
Frame Number High
).
Bit1
Bit1
R
R
Bit0
Bit0
R
R
USB Address:
USB Address:
00000000
00000000
Reset Value
Reset Value
0x0C
0x0D
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