MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 167

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.1 Entering Monitor Mode
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Table 10-1
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
If V
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC1 is high with V
the bus frequency will be a divide-by-four of the input clock. Holding the
PTC1 pin low when entering monitor mode causes a bypass of a divide-
by-two stage at the oscillator only if V
the CGMOUT frequency is equal to the CGMXCLK frequency, and the
OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is either V
requirements and conditions, including the PTC1 frequency divisor
selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
1. If $FFFE and $FFFF do not contain $FF (programmed state):
2. If $FFFE and $FFFF both contain $FF (erased state):
3. If $FFFE and $FFFF both contain $FF (erased state):
TST
– The external clock is 4.9152 MHz with PTC1 low or
– IRQ = V
– The external clock is 9.8304 MHz
– IRQ = V
– The external clock is 32.768 kHz (crystal)
– IRQ = V
is applied to IRQ and PTC1 is low upon monitor mode entry
9.8304 MHz with PTC1 high
pullup; PLL off)
32.768 kHz to an internal bus frequency of 2.4576 MHz)
shows the pin conditions for entering monitor mode. As
Monitor ROM (MON)
DD
TST
SS
(this setting initiates the PLL to boost the external
(this can be implemented through the internal IRQ
(PLL off)
TST
applied to IRQ upon monitor mode entry,
TST
is applied to IRQ. In this event,
DD
or V
SS
), then all port A pin
Functional Description
Monitor ROM (MON)
Data Sheet
167