MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 216

IC MCU 24K FLASH 8MHZ SPI 64LQFP

MC908LJ24CPBE

Manufacturer Part Number
MC908LJ24CPBE
Description
IC MCU 24K FLASH 8MHZ SPI 64LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Timer Interface Module (TIM)
Data Sheet
216
Address: T1CH0H, $0026 and T2CH0H, $0031
Address: T1CH0L, $0027 and T2CH0L $0032
Address: T1CH1H, $0029 and T2CH1H, $0034
Address: T1CH1L, $002A and T2CH1L, $0035
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 11-12. TIM Channel 0 Register High (TCH0H)
Figure 11-14. TIM Channel 1 Register High (TCH1H)
Figure 11-13. TIM Channel 0 Register Low (TCH0L)
Figure 11-15. TIM Channel 1 Register Low (TCH1L)
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Timer Interface Module (TIM)
14
14
6
6
6
6
6
6
13
13
5
5
5
5
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
12
12
4
4
4
4
4
4
MC68HC908LJ24/LK24 — Rev. 2.1
11
11
3
3
3
3
3
3
Freescale Semiconductor
10
10
2
2
2
2
2
2
9
9
1
1
1
1
1
1
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0

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