MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 422

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Voltage Inhibit (LVI)
22.4 Functional Description
Data Sheet
422
$FE0F
Addr.
Low-Voltage Inhibit Status
Register Name
Register
(LVISR)
Figure 22-2
The LVI is enabled out of reset. The LVI module contains a bandgap
reference circuit and comparator. Clearing the LVI power disable bit,
LVIPWRD, enables the LVI to monitor V
reset disable bit, LVIRSTD, enables the LVI module to generate a reset
when V
mode bit, LVISTOP, enables the LVI to operate in stop mode.
Reset:
Read: LVIOUT
Write:
Figure 22-1. LVI I/O Register Summary
FROM CONFIG2
DETECTOR
LVISEL[1:0]
LOW V
DD
Bit 7
V
DD
0
falls below a voltage, V
DD
shows the structure of the LVI module.
DEFAULT
ENABLED
Low-Voltage Inhibit (LVI)
Figure 22-2. LVI Module Block Diagram
= Unimplemented
LVIIE
TO LVISR
LVIOUT
6
0
FROM CONFIG1
LVIPWRD
V
V
DD
DD
LVIIF
> V
≤ V
5
0
TRIPR
TRIPF
DETECT
LATCH
EDGE
= 1
= 0
LVIIACK
FROM LVISR
LVIIACK
TRIPF
4
0
0
CLR
STOP INSTRUCTION
FROM CONFIG1
. Setting the LVI enable in stop
FROM LVISR
DD
LVIRSTD
TO LVISR
MC68HC908LJ24/LK24 — Rev. 2.1
LVIIE
3
0
0
LVIIF
voltage. Clearing the LVI
Freescale Semiconductor
0
0
2
FROM CONFIG1
LVISTOP
LVI RESET
LVI
INTERRUPT
REQUEST
1
0
0
Bit 0
0
0