MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 426

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Voltage Inhibit (LVI)
22.6 Low-Power Modes
22.6.1 Wait Mode
22.6.2 Stop Mode
Data Sheet
426
NOTE:
LVIIE — LVI Interrupt Enable Bit
LVIIF — LVI Interrupt Flag
LVIIACK — LVI Interrupt Acknowledge Bit
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets or interrupts, the LVI module can generate a reset or an
interrupt and bring the MCU out of wait mode.
If enabled in stop mode (LVISTOP = 1), the LVI module remains active
in stop mode. If enabled to generate resets or interrupts, the LVI module
can generate a reset or an interrupt and bring the MCU out of stop mode.
If enabled to generate both resets and interrupts, there will be no LVI
interrupts, as resets have a higher priority.
This read/write bit enables the LVIIF bit to generate CPU interrupt
requests. Reset clears the LVIIE bit.
This clearable, read-only flag is set whenever the LVIOUT bit toggles.
Reset clears the LVIIF bit.
Writing a logic 1 to this write-only bit clears the LVI interrupt flag,
LVIIF. LVIIACK always reads as logic 0.
1 = LVIIF can generate CPU interrupt requests
0 = LVIIF cannot generate CPU interrupt requests
1 = LVIOUT has toggled
0 = LVIOUT has not toggled
1 = Clears LVIIF bit
0 = No effect
Low-Voltage Inhibit (LVI)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor