MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 81

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4 Configuration Register 1 (CONFIG1)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
†† Reset by POR only.
Address:
The CONFIG1 register can be written once after each reset.
COPRS — COP Rate Select
LVISTOP — LVI Enable in Stop Mode
LVIRSTD — LVI Reset Disable
LVIPWRD — LVI Power Disable Bit
Reset:
Read:
Write:
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit
LVIRSTD disables the reset signal from the LVI module. (See
Section 22. Low-Voltage Inhibit
LVIPWRD disables the LVI module. (See
Inhibit
1 = COP time out period = 2
0 = COP time out period = 2
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
COPRS
$001F
Bit 7
Figure 5-2. Configuration Register 1 (CONFIG1)
Configuration Registers (CONFIG)
0
(LVI).)
LVISTOP LVIRSTD LVIPWRD
6
0
5
0
= Unimplemented
0
13
18
4
††
– 2
– 2
(LVI).)
(LVI).)
4
4
Configuration Register 1 (CONFIG1)
ICLK cycles
ICLK cycles
3
0
0
Configuration Registers (CONFIG)
Section 22. Low-Voltage
(COP).)
SSREC
2
0
STOP
1
0
Data Sheet
COPD
Bit 0
0
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