MC908LJ24CPKE Freescale Semiconductor, MC908LJ24CPKE Datasheet - Page 301

IC MCU 8BIT 24K FLASH 80-LQFP

MC908LJ24CPKE

Manufacturer Part Number
MC908LJ24CPKE
Description
IC MCU 8BIT 24K FLASH 80-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPKE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
48
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPKE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
interrupts share the same CPU interrupt vector. (See
not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition.
miss an overflow. The first part of
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
In this case, an overflow can be missed easily. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit.
avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.
SPSCR
OVRF
READ
READ
SPDR
SPRF
1
2
3
4
BYTE 1
Serial Peripheral Interface Module (SPI)
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
1
Figure 14-9. Missed Read of Overflow Condition
2
3
Figure 14-10
BYTE 2
4
Figure 14-9
Figure 14-9
illustrates this process. Generally, to
BYTE 3
5
5
6
7
8
Serial Peripheral Interface Module (SPI)
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
7
shows how it is possible to
shows how it is possible
BYTE 4
Figure
8
Error Conditions
14-11.) It is
Data Sheet
301

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