MC908LJ24CPKE Freescale Semiconductor, MC908LJ24CPKE Datasheet - Page 423

IC MCU 8BIT 24K FLASH 80-LQFP

MC908LJ24CPKE

Manufacturer Part Number
MC908LJ24CPKE
Description
IC MCU 8BIT 24K FLASH 80-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPKE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
48
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPKE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
The LVI trip point selection bits, LVISEL[1:0], select the trip point
voltage, V
points are shown in
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever
the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0).
After a power-on reset (POR) the LVI’s default mode of operation is 3V.
If a 5V system is used, the user must modified the LVISEL[1:0] bits to
raise the trip point to 5V operation. Note that this must be done after
every power-on reset since the default will revert back to 3V mode after
each power-on reset. If the V
when POR is released, the MCU will immediately go into reset. The LVI
in this case will hold the MCU in reset until either V
rising 3V trip point, V
approximately 0V which will re-trigger the power-on reset.
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the
configuration registers. See
(CONFIG)
occurs, the MCU remains in reset until V
V
Inhibit (LVI) Reset
LVI. The output of the comparator controls the state of the LVIOUT flag
in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIACK bits in
the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
TRIPR
, which causes the MCU to exit reset. See
TRIPF
for details of the LVI’s configuration bits. Once an LVI reset
Low-Voltage Inhibit (LVI)
, to be configured for 5V or 3V operation. The actual trip
for details of the interaction between the SIM and the
Section 24. Electrical
TRIPR
, which will release reset or V
Section 5. Configuration Registers
DD
supply is below the 3V mode trip voltage
DD
Specifications.
rises above a voltage,
9.4.2.5 Low-Voltage
Low-Voltage Inhibit (LVI)
DD
Functional Description
goes above the
DD
decreases to
Data Sheet
423

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