D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 115
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU.
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
ø
Internal
address bus
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction
TIER write cycle by CPU
TIER address
98
IMIA exception handling
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