D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 123
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.2 Register Descriptions
6.2.1 Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
When ABWCR contains H'FF (selecting 8-bit access for all areas), the H8/3002 operates in 8-bit
bus mode: the upper data bus (D
one bit is cleared to 0 in ABWCR, the H8/3002 operates in 16-bit bus mode with a 16-bit data bus
(D
mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.
ABWCR is not initialized in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access to the corresponding address areas.
Bits 7 to 0
ABW7 to ABW0
0
1
ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and
registers is fixed and does not depend on ABWCR settings.
Bit
Initial
value
Read/Write
15
to D
Modes 1, 3
Modes 2, 4
0
). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby
ABW7
Description
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
R/W
7
1
0
ABW6
R/W
15
6
1
0
to D
8
Bits selecting bus width for each area
ABW5
) is valid, and port 4 is an input/output port. When at least
R/W
5
1
0
106
ABW4
R/W
4
1
0
ABW3
R/W
3
1
0
ABW2
R/W
2
1
0
ABW1
R/W
1
1
0
ABW0
R/W
0
1
0
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