D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 373
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture
A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU
output. Figure 10-55 shows the timing.
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10-56 shows the timing.
ø
TIOCA
Input capture
signal
TOER
ITU output
pins
N: Arbitrary setting (H'C1 to H'FF)
Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example)
1
pin
ø
Address
TOCR
ITU output pin
ITU output
ITU output
N
T
1
TOCR address
357
H'C0
T
2
Generic
input/output
I/O port
T
3
Inverted
ITU output
N
ITU output
H'C0
I/O port
Generic
input/output
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