D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 476
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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In transmitting serial data, the SCI operates as follows.
•
•
Serial transmit data is transmitted in the following order from the TxD pin:
•
Figure 13-11 shows an example of SCI transmit operation using a multiprocessor format.
Figure 13-11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and
Serial
data
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
— Start bit:
— Transmit data:
— Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
— Stop bit:
— Mark state:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
1
TXI
request
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
One 0 bit is output.
One or two 1 bits (stop bits) are output.
Output of 1 bits continues until the start bit of the next transmit data.
7 or 8 bits are output, LSB first.
1 frame
Data
D7
0/1
Multi-
processor
bit
One Stop Bit)
TXI
request
Stop
bit
1
460
Start
bit
0
D0
D1
Data
D7
0/1
Multi-
processor
bit
TEI request
Stop
bit
1
Idle (mark)
state
1
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