D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 50
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 2-4 Arithmetic Operation Instructions (cont)
Instruction Size*
DIVXU
DIVXS
CMP
NEG
EXTS
EXTU
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
B/W
B/W
B/W/L
B/W/L
W/L
W/L
Function
Rd ÷ Rs
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits
16-bit quotient and 16-bit remainder.
Rd ÷ Rs
Performs signed division on data in two general registers: either
16 bits ÷ 8 bits
16-bit quotient and 16-bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
0 – Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
Rd (sign extension)
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
Rd (zero extension)
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Rd
Rd
Rd
8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits
Rd
Rd
33
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