M30622F8PGP#U5C Renesas Electronics America, M30622F8PGP#U5C Datasheet - Page 411
M30622F8PGP#U5C
Manufacturer Part Number
M30622F8PGP#U5C
Description
IC M16C MCU FLASH 64K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30622F8PGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30622F8PGP#U5CM30622F8PGP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PGP#U5CM30622F8PGP#D5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
1.10
REVISION HISTORY
May 28, 2003
Date
14-19 SFR is partly revised.
48-50 Figures 1.8.7 to 1.8.9 is partly revised.
Page
271
272
274
278
287
293
4-5
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33
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38
39
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46
47
51
52
53
55
58
60
2
Figure 1.27.7 is partly revised.
Explanation of “Interrupts” is partly revised.
Explanation of “Writing in the User ROM Space” is partly revised.
Table 1.27.4 is partly revised.
Explanation of “Read Array Command” is partly revised.
Explanation of “Program Command” is partly revised.
Figure 1.27.15 is partly revised.
Partly revised.
Table 1.1.1 is partly revised.
Table 1.1.2 and 1.1.3 is partly revised.
Note 1 is partly revised.
Explanation of “Hardware Reset 1” is partly revised.
Note 1 is added.
Figure 1.5.4 is partly revised.
Note 1 of Figure 1.5.5 is partly revised.
Figure 1.5.7 is partly revised.
Table 1.5.2 is partly revised.
Table 1.5.3 is partly revised.
Explanation of “1. Limitations on Stop Mode” is partly revised.
Explanation of “1. Limitations on WAIT instruction” is partly revised.
Figure 1.5.8 is partly revised.
Note is added.
Explanation of “Multiplexed Bus” is revised.
Explanation of “(2) Data Bus” is revised.
Explanation of “(7) Hold Signal” is revised.
Note 3 of Table 1.7.4 is added.
Note 4 of Table 1.7.5 is added.
Explanation of “(10) Software Wait” is revised.
Table 1.7.7 is revised.
Table of Figure 1.8.5 is revised.
Explanation is revised.
Explanation of “Clock Generation Circuit” is revised.
Figure 1.9.1 is revised.
Note of Figure 1.9.2 is revised.
Note 12 is added.
Explanation of “(1) Main clock” is partly revised.
Explanation of “(4) PLL Clock” is partly revised.
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
C - 4
Description
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