DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 736
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 8-Bit Timers (TMR)
13.6
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
13.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
13.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel
0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Rev.7.00 Mar. 18, 2009 page 668 of 1136
REJ09B0109-0700
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
cleared independently.
16-bit compare match conditions.
lower 8-bit compare match conditions.
Operation with Cascaded Connection
16-Bit Counter Mode
Compare Match Count Mode
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