DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 819
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2378BVFQ35V
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falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = ⏐ (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
2N
1
186 clocks
0
) – (L – 0.5) F –
(Using Clock of 372 Times the Bit Rate)
185
372 clocks
Start bit
371
Section 15 Serial Communication Interface (SCI, IrDA)
⏐D – 0.5⏐
0
N
D0
Rev.7.00 Mar. 18, 2009 page 751 of 1136
(1 + F) ⏐ × 100 [%]
185
371 0
REJ09B0109-0700
D1
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