M3062LFGPGP#U3C Renesas Electronics America, M3062LFGPGP#U3C Datasheet - Page 202
M3062LFGPGP#U3C
Manufacturer Part Number
M3062LFGPGP#U3C
Description
IC M16C/62P MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M3062LFGPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.9
UARTi Transmit/Receive Control Register 1 (i=0, 1)
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
b7 b6 b5 b4
NOTES :
1.
1. The U2LCH bit is enabled w hen the SMD2 to SMD0 bits in the U2MR register are set to “001b” (clock synchronous
The UiLCH bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial
I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I
data).
serial I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I
data).
Jan 10, 2006
b3 b2 b1 b0
U0C1 to U2C1 Registers
Bit Symbol
Bit Symbol
(b5-b4)
U2RRM
U2LCH
U2ERE
U2IRS
UiLCH
UiERE
TE
RE
TE
RE
U0C1, U1C1
—
Page 185 of 390
TI
RI
TI
RI
Symbol
U2C1
Symbol
Transmit Enable Bit
Transmit Buffer Empty Flag
Receive Enable Bit
Receive Complete Flag
Nothing is assigned. When w rite, set to “0”.
When read, these contents are indeterminate.
Data Logic Select Bit
Error Signal Output Enable Bit
Transmit Enable bit
Transmit Buffer Empty Flag
Receive Enable Bit
Receive Complete Flag
UART2 Transmit Interrupt Factor
Select Bit
UART2 Continuous Receive Mode
Enable Bit
Data Logic Select Bit
Error Signal Output Enable Bit
Bit Name
Bit Name
03A5h, 03ADh
Address
037Dh
Address
(1)
(1)
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in UiTB register
1 : No data present in UiTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in UiRB register
1 : Data present in UiRB register
0 : No reverse
1 : Reverse
0 : Output disabled
1 : Output enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in U2TB register
1 : No data present in U2TB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in U2RB register
1 : Data present in U2RB register
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : No reverse
1 : Reverse
0 : Output disabled
1 : Output enabled
2
2
C mode) or “110b” (UART mode, 9-bit transfer
C mode) or “110b” (UART mode, 9-bit transfer
After Reset
00XX0010b
After Reset
00000010b
Function
Function
17. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
—
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