DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 115
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.3.5
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Note:
5.3.6
SSIER selects the IRQ pins used to recover from the software standby state.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Bit Name
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
* Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Software Standby Release IRQ Enable Register (SSIER)
Initial Value R/W
0
0
0
0
0
0
0
0
Initial Value R/W
0
0
0
0
0
1
1
1
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
[Setting condition]
•
[Clearing conditions]
•
•
•
Description
Software Standby Release IRQ Setting
These bits select the IRQn pins used to recover from
the software standby state.
0: IRQn requests are not sampled in the software
1: When IRQn request occurs in the software standby
standby state (Initial value when n = 7 to 3).
state, the chip recovers from the software standby
state after the elapse of the oscillation settling time
(Initial value when n = 2 to 0).
When the interrupt source selected by ISCR
occurs
Cleared after reading condition1, when written as
0
When interrupt exception handling is executed
when low-level detection is set and IRQn input is
high
When IRQn interrupt exception handling is
executed while detecting the falling edge, rising
edge, or both
Rev.2.00 May. 28, 2009 Page 75 of 732
REJ09B0059-0200
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