DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 130
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.7
5.7.1
When an interrupt enable bit is cleared to mask interrupts, the masking becomes effective after
execution of the instruction.
When an interrupt enable bit is cleared by an instruction such as BCLR or MOV, if an interrupt is
generated during execution of the instruction, the interrupt concerned will still be enabled on
completion of the instruction, and so interrupt exception handling for that interrupt will be
executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Rev.2.00 May. 28, 2009 Page 90 of 732
REJ09B0059-0200
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Usage Notes
Contention between Interrupt Generation and Disabling
φ
Figure 5.6 Contention between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
TCIV exception handling
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