DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 142
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
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Quantity:
10 000
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6.4.2
The initial condition of the external address space is normal extended 3-state access space. The
space outside the on-chip ROM, on-chip RAM, internal I/O register, and their reserved areas are
available as the external address spaces. When the RAME bit in SYSCR is set to 1, the on-chip
RAM and its reserved area are enabled. However if the RAME bit is cleared to 0, the on-chip
RAM and its reserved area are ignored. When the RAME bit is 0, H'FF0000 to H'FF9FFF of the
on-chip RAM and its reserved area, becomes an external address area.
6.4.3
This LSI can output chip select signals (CS1 to CS3) for areas 0 to 3 respectively. The CS1 to CS3
signal outputs low or high level when the corresponding external space area is accessed. The chip
select signal’s output polarity can be controlled by the PNCCSn bit in BCRAn. Figure 6.2 shows
an example of CS1 to CS3 signal’s output polarity and output timing.
Selection of CS1 to CS3 signal output and I/O port input/output is set by the port function control
register (PFCR) bit for the port corresponding to the CS1 to CS3 pins. In external extended mode,
all of the CS1 to CS3 pins function as I/O ports after a reset. Therefore the corresponding PFCR
bits should be set to 1 when outputting signals CS1 to CS3. For details, refer to section 7, I/O
Ports.
Rev.2.00 May. 28, 2009 Page 102 of 732
REJ09B0059-0200
External Address Area
Chip Select Signals
Note: n = 1 to 3
(PNCCS = 0)
(PNCCS = 1)
Address bus
Figure 6.2 CSn Signal Output Polarity and Output Timing
T 1
External address of area n
Bus cycle
T 2
T 3
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