DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 57
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.1.2
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
• Expanded address space
• Enhanced addressing
• Enhanced instructions
• Higher speed
Note: Normal mode is not available in this LSI.
2.1.3
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
• Additional control register
• Enhanced instructions
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Basic instructions execute twice as fast.
One 8-bit and two 32-bit control registers have been added.
Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Differences from H8/300 CPU
Differences from H8/300H CPU
Rev.2.00 May. 28, 2009 Page 17 of 732
REJ09B0059-0200
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