DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 99
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2437FV
Manufacturer:
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- Current page: 99 of 776
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Notes: 1. Lower 16 bits of the address.
4.3
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 15,
Watchdog Timer (WDT).
The interrupt control mode is 0 immediately after reset.
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception-handling vector address is read and transferred to the PC, and program
Figure 4.1 shows an example of the reset sequence.
Exception Source
Internal interrupt*
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
2. Not available in this LSI.
3. Not available in this LSI. Becomes reserved for system use.
4. For details on internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Reset
Reset exception handling
Vector Table.
4
Vector Number
24
127
⎜
Normal Mode*
H'0030 to H'0031
H'00FE to H'00FF
⎜
Rev.2.00 May. 28, 2009 Page 59 of 732
Vector Address*
2
Advanced Mode
H'0060 to H'0063
H'01FC to H'01FF
REJ09B0059-0200
1
⎜
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