M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 260
M306N4FGGP#U3
Manufacturer Part Number
M306N4FGGP#U3
Description
IC M16C/6N4 MCU FLASH 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Specifications of M306N4FGGP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
I2C/UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 19.21 Timing of Transmit Sequence
19.15.2 Transmission
Figure 19.21 shows the Timing of Transmit Sequence.
(1) If the TrmReq bit in the CiMCTLj register (i = 0, 1, j = 0 to 15) is set to 1 (transmission slot) in the bus
(2) If the arbitration is lost after the CAN module starts the transmission, bits TrmActive and TrmState are
(3) If the transmission has been successful without lost in arbitration, the SentData bit in the CiMCTLj
(4) When starting the next transmission, set bits SentData and TrmReq to 0. And set the TrmReq bit to 1
idle state, the TrmActive bit in the CiMCTLj register and the TrmState bit in the CiSTR register are set
to 1 (transmitting/transmitter), and CAN module starts the transmission.
set to 0.
register is set to 1 (transmission is successfully completed) and TrmActive bit is set to 0 (waiting for
bus idle or completion of arbitration). And when the interrupt enable bits in the CiICR register = 1
(interrupt enabled), CANi successful transmission interrupt request is generated and the MBOX (the
slot number which transmitted the message) and TrmSucc bit in the CiSTR register are changed.
after checking that bits SentData and TrmReq are set to 0.
Apr 14, 2006
transmission interrupt
i = 0, 1
j = 0 to 15
CANi successful
TrmActive bit
SentData bit
TrmState bit
TrmSucc bit
TrmReq bit
MBOX bit
page 236 of 376
CTX
(1)
(1)
(1)
SOF
(2)
(2)
ACK
EOF
(3)
(3)
(3)
IFS
Transmission slot No.
SOF
(4)
19. CAN Module
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