HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 190
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Instruction Descriptions
6.1.25
Class: Delayed branch instruction
Format
JMP
Description: Branches unconditionally to the address specified by register indirect addressing.
The branch destination is an address specified by the 32-bit data in general register Rm.
Note: Since this is a delayed branch instruction, the instruction after JMP is executed before
Operation:
Example:
Rev. 5.00 Jun 30, 2004 page 174 of 512
REJ09B0171-0500O
JMP(long m)
{
}
JMP_TABLE: .data.l
TRGET:
unsigned long temp;
temp=PC;
PC=R[m]+4;
Delay_Slot(temp+2);
@Rm
branching. No interrupts or address errors are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
JMP (Jump): Branch Instruction
Abstract
Rm
MOV.L
JMP
MOV
.align
.................
ADD
/* JMP @Rm */
PC
JMP_TABLE,R0
@R0
R0,R1
4
TRGET
#1,R1
Code
0100mmmm00101011 2
; Address of R0 = TRGET
; Branches to TRGET
; Executes MOV before branching
; Jump table
;
Branch destination
Cycle T Bit SH-1 SH-2
—
Instructions
Applicable
SH-
DSP
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