HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 425
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
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10 000
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This section describes the operation of the pipelines for each instruction. This information is
provided to allow calculation of the required number of CPU instruction execution states (system
clock cycles).
7.1
7.1.1
Pipelines are composed of the following five stages:
1. IF (Instruction fetch)
2. ID (Instruction decode)
3. EX (Instruction execution)
4. MA (Memory access)
5. WB/DSP (W/D) (Write back (CPU core) or DSP (DSP unit))
These stages flow with the execution of the instructions and thereby constitute a pipeline. At a
given instant, five instructions are being executed simultaneously. The basic pipeline flow is as
shown in figure 7.1. The period in which a single stage is operating is called a slot and is indicated
by two-way arrows (
All instructions have at least the 3 stages IF, ID and EX, but not all have stages MA and WB/DSP.
The way the pipeline flows also varies with the type of instruction. Some pipelines differ,
however, because of contention between IF and MA.
Fetches instruction from the memory where the program is stored.
Decodes the instruction fetched.
Does data operations and address calculations according to the results of decoding.
Accesses data in memory. Generated by instructions that involve memory access, with some
exceptions.
Write Back: Returns the results of the memory access (data) to a register. Generated by
instructions that involve memory loads, with some exceptions.
DSP: Does operations using the DSP unit’s ALU and MAC. Also, the results of memory
accesses (data) are returned to registers; not generated during writes to memory or no operation
(NOP).
Basic Configuration of Pipelines
The Five-Stage Pipeline
Section 7 Pipeline Operation
.
Rev. 5.00 Jun 30, 2004 page 409 of 512
Section 7 Pipeline Operation
REJ09B0171-0500O
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