HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 456
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Pipeline Operation
Multiply/Accumulate Instruction (SH-1 CPU): Includes the following instruction type:
MAC.W
@Rm+, @Rn+
: Slot
Instruction A
IF
ID
EX
MA
MA
mm
mm
Next instruction
IF
—
ID
EX
MA
WB
Third instruction in series
IF
ID
EX
MA
WB
......
Figure 7.23 Multiply/Accumulate Instruction Pipeline
The pipeline has seven stages: IF, ID, EX, MA, MA, mm, and mm. The second MA reads the
memory and accesses the multiplier. mm indicates that the multiplier is operating. mm operates for
two cycles after the final MA ends, regardless of slot. The ID of the instruction after the MAC.W
instruction is stalled for 1 slot. The two MAs of the MAC.W instruction, when they contend with
IF, split the slots as described in Section 7.2.1, Contention between Instruction Fetch (IF) and
Memory Access (MA).
When an instruction that does not use the multiplier comes after the MAC.W instruction, the
MAC.W instruction may be considered to be a five-stage pipeline instruction of IF, ID, EX, MA,
MA. In such cases, the ID of the next instruction simply stalls one slot and thereafter operates like
a normal pipeline. When an instruction that uses the multiplier comes after the MAC.W
instruction, however, contention occurs with the multiplier, so operation is different from normal.
This occurs in the following cases:
1. When a MAC.W instruction is located immediately after another MAC.W instruction
2. When a MULS.W instruction is located immediately after a MAC.W instruction
3. When an STS (register) instruction is located immediately after a MAC.W instruction
4. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
5. When an LDS (register) instruction is located immediately after a MAC.W instruction
6. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction
Rev. 5.00 Jun 30, 2004 page 440 of 512
REJ09B0171-0500O
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