HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 489
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Multiplication Instructions (SH-2 CPU, SH-DSP): Include the following instruction types:
Operation: The pipeline has six stages: IF, ID, EX, MA, mm, and mm (figure 8.62). The MA
accesses the multiplier. The mm indicates that the multiplier is operating. The mm operates for
two cycles after the MA ends, regardless of the slot. The MA of the MULS.W instruction, when it
contends with IF, splits the slot as described in Section 7.4, Contention Between Instruction Fetch
(IF) and Memory Access (MA).
When an instruction that does not use the multiplier comes after the MULS.W instruction, the
MULS.W instruction may be considered to be four-stage pipeline instructions of IF, ID, EX, and
MA. In such cases, it operates like a normal pipeline. When an instruction that uses the multiplier
is located after the MULS.W instruction, however, contention occurs with the multiplier, so
operation is not as normal. This occurs in the following cases:
1. When a MAC.W instruction is located immediately after a MULS.W instruction
2. When a MAC.L instruction is located immediately after a MULS.W instruction
3. When a MULS.W instruction is located immediately after another MULS.W instruction
4. When a DMULS.L instruction is located immediately after a MULS.W instruction
5. When an STS (register) instruction is located immediately after a MULS.W instruction
6. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
7. When an LDS (register) instruction is located immediately after a MULS.W instruction
8. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction
MULS.W
MULU.W
Third instruction
Next instruction
Rm, Rn
Rm, Rn
MULS.W
Figure 7.62 Multiplication Instruction Pipeline
.....
IF
ID
IF
EX
ID
IF
MA mm mm
EX
ID
MA
EX
Rev. 5.00 Jun 30, 2004 page 473 of 512
WB
MA
WB
Section 7 Pipeline Operation
: Slot
REJ09B0171-0500O
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